Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Reexamination Certificate
1999-05-27
2001-08-14
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
C345S503000, C710S108000
Reexamination Certificate
active
06275240
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of installing an upgrade graphics device in the presence of a previously installed graphics device.
BACKGROUND OF THE INVENTION
High performance graphics devices are becoming increasingly important in today's computer systems. Computer system manufacturers commonly install graphics accelerators on add-in cards that plug into connectors that provide connection to a graphics bus such as an accelerated graphics port (AGP) bus. Graphics accelerators are also commonly installed by soldering the component directly onto computer system motherboards. The add-in card method provides the computer system manufacturer and the end user a means for installing a newer model graphics accelerator. One can simply remove the old add-in card and install a new one. The add-in card method has a drawback in that the add-in card method is more expensive than the solder-down method. The add-in card also uses more space than a device soldered directly onto the motherboard.
The solder-down method provides a cost savings over the add-in card method, but has the disadvantage of not providing a method for upgrading the graphics accelerator. If a computer system manufacturer wishes to change to a different graphics accelerator, the computer system manufacturer must redesign the motherboard. Further, the AGP bus is meant to be a point-to-point interconnect between a system memory controller and a single graphics device, and prior computer systems that utilize an AGP bus are not able to provide an upgrade option when a graphics device is already soldered onto the motherboard.
An AGP graphics device may have the ability to operate in one or more of several data transfer modes, including 2× mode and 4× mode. The 2× mode allows the transfer of 8 bytes of data per clock cycle using a pair of data strobe signals. The 4× mode allows the transfer of 16 bytes per clock cycle using 2 pairs of data strobe signals.
A prior 2× mode AGP graphics device normally includes input/output buffers for two address/data strobe signals (AD_STB
0
and AD_STB
1
) and an input buffer for a sideband strobe signal (SB_STB). An AGP bus that allows 4X mode operation provides compliments of the above strobe signals (AD_STB
0
#, AD_STB
1
#, and SB_STB#) in addition to the above strobe signals. When the prior 2× mode AGP graphics device is installed on the AGP bus capable of 4× mode operation, the strobe compliment signals in prior systems are not connected at the prior 2× mode AGP graphics device. If an upgrade 4× mode AGP graphics device is installed on the 4× mode capable AGP bus in parallel with the prior 2× mode AGP device, a situation is created where the AD_STB
0
, AD_STB
1
, and SB STB signals have three capacitive loads (one at a memory controller, one at the prior 2× mode AGP graphics device, and one at the upgrade 4× mode AGP graphics device) and the AD_STB
0
#, AD_STB
1
#, and SB_STB# signals have two capacitive loads (one at the memory controller and one at the upgrade 4× mode AGP graphics device). This difference in capacitive loading between the strobe signals and their compliments would have a negative impact on graphics bus timing relationships, and therefor a negative impact on system reliability.
SUMMARY OF THE INVENTION
A graphics device for maintaining load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The graphics device includes a bus interface unit including a plurality of bus signal buffers to couple the graphics device to a graphics bus. The graphics device further includes a load balancing bus signal buffer to further couple the graphics device to the graphics bus, the load balancing bus signal buffer to provide load balancing on the graphics bus when an upgrade graphics device is installed.
REFERENCES:
patent: 5799204 (1998-08-01), Pesto, Jr.
patent: 5884053 (1999-03-01), Clouser et al.
patent: 5892964 (1999-04-01), Horan et al.
patent: 6141021 (2000-10-01), Bickford et al.
patent: 6170029 (2001-01-01), Kelley et al.
Chauhan Ulka J.
Intel Corporation
Wells Calvin E.
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