Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
1999-10-13
2002-07-02
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S227000, C712S228000, C703S026000, C711S205000, C711S202000, C711S206000
Reexamination Certificate
active
06415379
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to apparatus and a method for improving the performance of a microprocessor in executing programs translated from programs designed for execution by a different processor.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but fast host processor (called a “morph host”) and software (referred to as “code morphing software”) to execute application programs designed for a target processor having an instruction set different than that of the morph host processor. The morph host processor executes the code morphing software which translates the target application programs dynamically into host processor instructions able to accomplish the purpose of the target application programs. As the instructions are translated, they are stored in a translation buffer where they may be accessed without further translation. Although the initial translation of a program is slow, once translated, many of the steps normally required for hardware to execute a program are eliminated. The new microprocessor has demonstrated that a simple fast processor designed to expend little power is able to execute translated “target” instructions at a rate equivalent to that of the “target” processor for which the programs were designed.
Complicating the problem of translation are the various interruptions and exceptions which are carried out by the hardware of a target computer and its operating system in order for the computer system to operate. When a target exception is taken during the operation of a target computer, state of the computer at the time of the exception must be saved typically by calling a microcode sequence to accomplish the operation, the correct exception handler must be retrieved, the exception must be handled, then the correct point in the program must be found for continuing with the program. Often this requires that the program revert to the state of the target computer at the point the exception was taken. The results provided by the hardware and software of the target computer to accomplish these operations must somehow be provided by the process of translation so that the morph host processor is able to correctly respond to these exceptions.
In order to be able to run programs designed for other processors at a rapid rate, the morph host processor includes a number of hardware enhancements. One of these enhancements is a gated store buffer which stores temporarily memory stores resulting from the execution of the translated sequence of instructions in the translation buffer. A second enhancement is a set of host registers (in addition to normal working registers) which store state of the target processor at the beginning of any sequence of target instructions being translated. Sequences of target instructions are translated into host instructions and executed. The sequences begin and end at points at which target state is known. If the translated instructions execute without raising an exception, the memory stores generated by the execution of the translated host instructions are stored in memory (committed to memory) by a commit instruction; and the registers holding the target state are updated to the target state at the point at which the sequence completed.
However, if an exception occurs during the execution of the sequence of host instructions, processing stops; and the entire operation may be returned to the beginning of the sequence of target instructions at which known state of the target processor exists. This allows rapid and accurate handling of exceptions incurred while dynamically translating and executing instructions.
It will be noted that the method by which the new microprocessor handles the execution of translations by placing the effects generated by execution in temporary storage until execution of the translation has been completed is effectively a rapid method of speculating. The new microprocessor, in fact, uses the same circuitry for speculating on the outcome of other operations. For example, by temporarily holding the results of execution of instructions reordered by a software scheduler from naively translated instructions, more aggressive reordering may be accomplished than has been attempted by the prior art. When such a reordered sequence of instructions executes to produce a correct result, the memory stores resulting from execution of the reordered sequence may be committed to memory and target state may be updated. If the reordered sequence generates an exception while executing, then the state of the processor may be rolled back to target state at the beginning of the sequence and a more conservative approach taken in executing the sequence.
One of the most advantageous features of the new microprocessor is its ability to link together long sequences of translated instructions. Once short sequences of target instructions have been translated and found to execute without exception, it is possible to link large numbers of these short sequences together to form long sequences of instructions. This allows a translated program to be executed at great speed because the microprocessor need not go through all of the steps (such as looking up each of the shorter translated sequences) normally taken by hardware processors to execute instructions. Even more speed may be attained than might be expected because, once long sequences are linked, it is often possible for an optimizer to eliminate many of the steps from the long sequences without changing the results produced. Hardware optimizers have never been able to optimize sequences of instructions long enough to allow the patterns which allow significant optimization to become apparent.
Whenever a processor is executing instructions, it is running in some particular mode which has various characteristics. The instructions of an application must be executed in the correct mode to consistently produce the correct results. These characteristics of a mode are effectively background for the instructions and may be considered to be a part of the instructions. As a processor executes instructions, certain of those instructions may change the characteristics and thus the mode of operation. This requires that a number of characteristics of the microprocessor be set differently to handle these different modes. The characteristics of machine state which must be set correctly in order for instructions to provide the correct result are typically referred to as the context in which the instructions execute. Context may be said to summarize the current state of the machine that is necessary to produce the correct result from the execution of instructions.
A major problem which the new microprocessor faces in translating sequences of instructions designed for a target processor having a first instruction set into a sequence of host instructions of a different instruction set is caused by the need to maintain context while translating and running.
There are a myriad of different things which can constitute context in executing a program. The recitation of just a few of the many elements which can constitute context illustrates just how complicated the problem is. Those skilled in the art will understand that there are literally hundreds of possible items of context.
Many microprocessors are designed to function with application programs having instructions of eight bit, sixteen bit, and thirty-two bit words lengths depending on the capability of the operating system in use. Often the same instructions are utilized with applications written with instructions of different word lengths. However, if the microprocessor attempts to execute sixteen bit instructions while its characteristics are set for executing thirty-two bit instructions, the instructions will probably not execute correctly. Thus, instruction word length can be considered as target processor context for execution purposes.
As another example, instructions execute at different levels of permission.
Bedichek Robert
Cmelik Robert
Keppel David
King Stephen L.
Pan Daniel H.
Transmeta Corporation
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