Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing
Reexamination Certificate
1999-01-14
2002-08-13
Vu, Viet D. (Department: 2758)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
C709S220000, C709S224000, C709S241000
Reexamination Certificate
active
06434626
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the field of computer networks. In particular, but not by way of limitation, the present invention relates to a method and apparatus for reducing latency associated with monitoring the performance of nodes organized in a network that allows multicasting. By way of example, the present invention is directed to a System Area Network (SAN) that is compliant with Intelligent Input/Output (I
2
O) architectures.
BACKGROUND OF THE INVENTION
With the proliferation of high performance computer workstations in virtually every workplace and the increased demand for interconnectivity, computer networks have experienced corresponding growth. Computer networks are a driving force in increasing workplace productivity by allowing resources to be shared efficiently among multiple users and allowing alternate or backup resources to be used when other resources fail or become congested with traffic. Networks further and facilitate the efficient transfer of large amounts of data between network nodes depending on dynamic traffic conditions and node health. As networks become more complex and greater numbers of elements are added and serviced by individual network servers, the factors which impact the efficiency of data transfer therefore increase in number. Moreover, networks of networks are becoming a more common part of the networking environment leading to ever increasing degrees of complexity for individual network servers to manage.
Along with data transfer efficiency, critical network management functions such as performance monitoring may be compromised by increasing demand for bandwidth and a shift to more data-driven computing. Driven by factors including increases in processor speeds, increasing demand for open architecture designs, and I/O bottlenecks created by bus bandwidth limitations and non standard interfaces between device drivers and operating systems, a standardized I/O architecture specification (called Intelligent Input/Output architecture) has been developed by an industry group known as the I
2
O Special Interest Group (SIG). The I
2
O specification includes, among other things, models for creating device and operating-system-independent network communications.
Because the teachings of the present invention may be better exemplified in relation to the I
2
O architecture, a brief overview thereof is provided hereinbelow. Essentially, the I
2
O architecture uses a “split driver” model wherein a messaging layer is inserted for dividing a single device driver into two separate modules—an Operating System Service Module (OSM) and a Downloadable Driver Module (DDM). The OSM comprises the portion of the device driver that is specific to the operating system. The OSM interfaces with the operating system of the computer system, which may also be referred to in the art as the “host operating system”, and is executed by the host CPU or processor. Typically, a single OSM may be used to service a specific class of peripherals or adapters. For example, one OSM would be used to service all block storage devices, such as hard disk drives and CD-ROM drives. As described, in the split driver model, the DDM provides an interface between the specific device and the OSM. The DDM includes the peripheral-specific portion of the device driver that understands how to interface to the particular peripheral hardware, while providing support for standard calls to the devices of a device class by the operating system by way of the OSM. To execute the DDM, an I
2
O Input/Output Processor (IOP) is added to the computer system. A single IOP may be associated with multiple peripherals, each controlled by a particular DDM, and containing its own operating system such as, for example, the I
2
O Real-Time Operating System (iRTOS). The DDM directly controls the peripheral, and is executed by the IOP under the management of the iRTOS.
A DDM may typically include a Hardware Device Module (HDM) that directly interfaces with the peripheral and is responsible for general device control and for managing data transfer to and from the device. A DDM may also include an Intermediate Service Module (ISM) which is an additional software interface to the HDM. Thus the ISM may typically form a custom layer between the OSM and HDM that generally resides on the IOP. In the I
2
O specification, the ISM is called out to allow for any special purpose processing that is desired which falls outside of standard OSM to DDM messaging.
A system which is compliant with the I
2
O specification uses a message passing model in general operation. When the CPU seeks to read or write to an adapter or peripheral in an I
2
O system, the host operating system makes what is known as a “request”. The OSM translates the request by the host operating system and, in turn, generates a message. The OSM sends the message across the messaging layer to the DDM associated with the peripheral which processes it appropriately and responds according to the contents of the message. If a special purpose ISM is present, the ISM may process the message prior to the message being passed to the DDM. Upon completion of whatever action the received message specifies, the DDM responds to the OSM by sending an appropriate response message through the messaging layer. Actions may include, but are not limited to, performing a read or write operation performing a data transfer, or reporting device status. The response may include an acknowledgment that the action was performed, the status of the action underway, an error message and the like. By executing the DDM and the ISM if included, on the IOP, time-consuming information transfers to and from the peripheral hardware are off-loaded from the CPU of the server to the IOP. By off-loading I/O processing to the IOP, the server CPU is no longer diverted for inordinate amounts of time during an I/O transaction. Moreover, because the IOP is dedicated to processing I/O transactions, data transfers are carried out more efficiently and faster.
In current implementations of the I
2
O specifications, once a typical I/O device is configured the I/O device typically receives only a small subset of message types which typically involve relatively simple data move operations. While the I
2
O specification guides the compatibility of systems and devices in a diverse product market, it is important to note that systems may be I
2
O compatible yet provide features which better accomplish the goals set forth as the motivation behind I
2
O, that is, greater I/O independence and data transfer capacity and processor unburdening. Moreover, it is possible to achieve the goals of greater independent I/O data transfer capacity in a system which is not strictly I
2
O compliant.
Another solution for relieving network bottlenecks and achieving scalability is to provide a clustered network environment wherein a variety of components like servers, disk drives, tape drives, etc., are integrated into a system-wide architecture such as a System Area Network (SAN). SAN architectures, for example, a fabric network, provide a low latency interconnect between servers and devices and can be configured for I
2
O compliance. SAN architecture is based on message passing between servers and devices. SAN technology employs the server processor to process data transfer requests between network elements and then allow data transfers to occur under control of dedicated hardware thus reducing server processor overhead to a minimum. In a SAN architecture, a network transport layer may be implemented on a dedicated hardware platform, typically an I/O processor (IOP), which allows a processor to be connected to a scalable switching fabric. A SAN server can then be expanded to add data paths which effectively increase the overall bandwidth of the switching fabric by increasing the number of point-to-point datapaths which can be used to carry data between nodes. Thus, large numbers of nodes which may be clients, other servers, or other network devices such as disk towers, and the like may be controlled by a server. Fur
Prakash Ramkrishna V.
Whiteman William F.
Compaq Information Technologies Group L.P.
Fletcher Yoder & Van Someren
Vu Viet D.
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