Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1997-12-23
2001-02-27
Brier, Jeffery (Department: 2775)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S001300, C463S042000
Reexamination Certificate
active
06195086
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of raster scan display controllers. Specifically, the present invention pertains to synchronization of multiple raster scan display controllers.
DESCRIPTION OF RELATED ART
Images are drawn on prior art raster display systems, such as television and computer displays, by tracing a plurality of horizontal raster scan lines, each scan line comprising a row of individual pixels. The entire image is scanned out sequentially by a video controller one scan line at a time from the top left corner of the display screen to the bottom right corner of the display screen. Clocking circuitry, typically included with the video controller, is used to maintain precise control over the rate at which scan lines are traced. Typically, a crystal oscillator is used as a clock source for this clocking circuitry. Although oscillators and other clock sources usually provide a highly accurate clock source for a particular display system, small variations in the timing between different oscillators invariably occur. These variations can be aggravated by environmental conditions such as temperature. Thus, it can be expected that two identical, but independent, display systems initially started at the same instant will eventually drift out of synchronization to the point where one of the display systems will eventually get a full frame ahead of the other. These prior art systems do not provide a means for synchronizing the raster scan process among a plurality of independent raster display systems without driving each system with a precise common clock source.
Prior art raster display systems operate in two fundamental types of refresh modes: interlaced and non-interlaced mode. Interlaced mode is used in broadcast television (NTSC, PAL, and SECAM) and in raster displays designed to drive standard television monitors. NTSC (National Television System Committee), PAL (Phase Alternate Line), and SECAM are well known raster display design and operational standards. For NTSC, the refresh cycle in interlaced mode is broken into phases (known as “fields”), each phase lasting {fraction (1/60)} of a second ({fraction (1/50)} of a second for PAL and SECAM); thus, a full NTSC refresh cycle lasts {fraction (1/30)} of a second ({fraction (1/25)} of a second for PAL/SECAM). All odd numbered scan lines are displayed in the first phase and all even numbered scan lines are displayed in the second phase. The purpose of the interlaced scan mode is to place some new information in all areas of the screen at a 60 Hz rate; because, a 30 Hz refresh rate tends to cause an irritating flicker. The net effect of interlacing is to produce a picture whose effective refresh rate is perceptively like 60 Hz while actually running at 30 Hz. This technique works as long as adjacent scan lines display similar information. An image consisting of dissimilar horizontal lines on alternating scan lines, such as often occurs in computer-generated images, causes an unpleasant line flicker effect.
When an NTSC display is refreshed in a non-interlaced mode (as is common with home computers and video games), the refresh cycle consists of scanning just the first phase or just the odd numbered scan lines at a 60 Hz rate. Alternatively, just the even numbered scan lines are refreshed at a 60 Hz rate. The unrefreshed scan lines in a non-interlaced mode are displayed as black or absent any image features. The non-interlaced mode is commonly used in home computers and video game displays because line flicker problems cannot be tolerated.
Most video game displays run independently from any external clock source. Thus, using prior art synchronization techniques, multiple video game displays can not be synchronized to each other. Even advanced video games and computer systems that can accept an external clock source for synchronization require such clock to be extremely precise; accurate to the order of one part per 10 million. In many situations, such a precise clock cannot be feasibly provided (e.g. if only a telephone modem connection exists between the systems).
Thus, a better means and method for synchronizing closed free-running systems is needed.
SUMMARY OF THE INVENTION
The present invention is a means and method for synchronizing closed free-running systems, such as graphics systems, with no external synchronization signals required. Video games and most computer display controllers are closed free-running systems. Because most such systems have the means to switch between an interlaced and non-interlaced operation, and because interlaced and non-interlaced modes have a relative timing variation, the timing between two or more such closed free-running systems can be synchronized. This method allows synchronization with an imprecise timing reference. The present invention is specifically applicable to maintaining frame synchronization between two video games or computer systems connected via a modem link.
The present invention is similar to a phase-locked loop. The vertical display timing is the free-running oscillator and the interlaced
on-interlaced mode transition is used as the timing adjustment means. The actual arrival time of data in a communication medium connecting two systems being synchronized is used in relation to an expected arrival time to provide the clock reference.
Television studios have distributed synchronized signals that are accurate on the order of 1 part per 100 million (i.e. 10 us clock precision). The present invention operates with timing references as slow as 300 Hz with an accuracy no better than 1 part per 525 (about 2 msec clock accuracy). Also, the present invention can achieve synchronization by use of a timing reference which is asynchronous to both raster timings (e.g. 2400 bps modem bit clock). It is a further advantage of the present invention that the implementation of the synchronization apparatus of the present invention requires a minor amount of processing to maintain synchronization, and no external hardware needs to be added to the display controller. It is a further advantage of the present invention that the implementation of the synchronization apparatus of the present invention does not noticeably disturb the displayed image while maintaining synchronization. The brief transitions between alternate timing modes cannot typically be perceived by a human viewer. Television and other raster devices are not disrupted by the brief transitions between alternate timing modes. It is a further advantage of the present invention that the implementation of the synchronization apparatus of the present invention works with either normally interlaced or normally non-interlaced displays. Normally non-interlaced displays are switched to interlaced mode briefly to maintain synchronization. Normally interlaced displays are switched to non-interlaced mode briefly to maintain synchronization. Because both display generators are crystal-controlled, the display generators will be fairly stable relative to each other and will only need brief, periodic adjustments. Typically, several hundred normal frames are displayed before a single frame of the alternate mode is switched in. It is a further advantage of the present invention that the implementation of the synchronization apparatus of the present invention is tolerant to the loss of a timing reference for short intervals. Often in video games, for example, the vertical blanking interrupt is turned off for brief periods of time. This occurs, for example, while a new screen is being set up during a transition. Although the timing of the two display controllers may drift during this time, their crystal references guarantee they won't drift very far. Thus, several seconds can safely elapse before vertical blanking interrupts are restored. When vertical blanking interrupts are restored, the present invention pulls the two displays exactly into synchronization again. Typically, only two or three alternate frames (as opposed to the usual one frame) are needed to restore synchronization within-tolerance. Finall
Perlman Stephen G.
Roskowski Steven G.
Bell Paul A.
Brier Jeffery
HearMe
Wilson Sonsini Goodrich & Rosati
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