Method and apparatus for logical simulation

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364200, 3642212, 3642643, G06F 1520, G06F 944

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active

050519417

ABSTRACT:
A method of logic simulation for simulating operation of a logic circuit by using basic signal values corresponding to states of output signals of elements of the logic circuit to be simulated and expanded signal values including the basic signal values. The logic circuit to be simulated is divided into a portion to be simulated by using the basic signal values and the expanded signal values and a portion to be simulated by using the basic signal values without using the expanded signal values. The elements for which definition of calculation method for output signal values for the input signal values including the expanded signal values is not easy are included in the latter portion, and other elements are included in the former portion. A virtual signal conversion element for converting the expanded signal into the basic signal is provided at a position where a signal is sent from the former portion to the latter portion so that the expanded signal value outputted from the element of the former portion is converted into the basic signal value before it is sent to the element of the latter portion.

REFERENCES:
patent: 4342093 (1982-07-01), Miyoshi
patent: 4587625 (1986-05-01), Marino, Jr. et al.
patent: 4635218 (1987-01-01), Widdoes, Jr.
patent: 4694411 (1987-09-01), Burrows
patent: 4725971 (1988-02-01), Doshi et al.

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