Method and apparatus for logic equivalence verification, and...

Details Method and apparatus for logic equivalence verification, and... Method and apparatus for logic equivalence verification, and...

2011-06-28

2011-06-28

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S107000, C716S111000

Reexamination Certificate

active

07971165

ABSTRACT:
A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.

REFERENCES:
patent: 7266790 (2007-09-01), Pandey et al.
patent: 2004/0098683 (2004-05-01), Maruyama et al.
patent: 2004/0261043 (2004-12-01), Baumgartner et al.
patent: 2007/0234242 (2007-10-01), Inui et al.
patent: 2001-67379 (2001-03-01), None

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