Patent
1995-05-02
1996-11-05
Teska, Kevin J.
H04L 1228
Patent
active
055727344
ABSTRACT:
A master bus interconnecting multiple masters is coupled via any number of intervening buses to a slave bus interconnecting multiple slaves and masters. A lock arbiter signal is passed to each successive bus-to-bus interface concurrent with an instruction issued by a master accessing a slave on a remote bus. Address, control, data, and lock arbiter signals are buffered in successive intervening bus-to-bus interfaces including the bus-to-bus interface to the slave bus. The lock arbiter signal when received by the slave bus-to-bus interface will set a lock arbiter register within bus slave bus-to-bus interface. Setting the lock arbiter register once a target slave has been accessed prevents any other master operating on the remote bus from using the remote bus or connecting to the remote bus-to-bus interface. Indivisible sequences of bus operations targeted for the target slave may be confined to the bus to which the target slave is coupled although intervening buses and bus-to-bus interfaces may be disconnected and reassigned pending completion of the indivisible sequence.
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MacAvoy Neil
Narad Charles E.
Fiul Dan
Sun Microsystems Inc.
Teska Kevin J.
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