Method and apparatus for limiting pin driver offset voltages

Details Method and apparatus for limiting pin driver offset voltages Method and apparatus for limiting pin driver offset voltages

1993-05-03

1994-12-27

Cosimano, Edward R.

Excavating

324 731, 364579, G05B 2302, G01R 1508

Patent

active

053772024

ABSTRACT:
A test equipment pin driver having a main output channel including a pulse forming circuit, a buffer and an output amplifier connected in series. The pulse forming circuit provides pulses that are timed to a data input signal, and the buffer passes the pulses to the amplifier which produces driver pulses adapted to be transmitted to a device under test. The high and low voltage levels of the driver pulses are made substantially the same as programmed high and low voltages by providing scaled replicas of the buffer and amplifier, and using closed loop compensation to accurately drive the replica outputs to the high and low programmed voltages, respectively. The replicas mirror the DC performance of the buffer and amplifier of the main output channel, and clamping voltages are provided from the closed loops to enable operation of the main output channel in a manner that produces driver pulses with the programmed high and low voltage levels.

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