Method and apparatus for level shifting approach with...

Details Method and apparatus for level shifting approach with... Method and apparatus for level shifting approach with...

2001-06-27

2003-01-28

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

Reexamination Certificate

active

06512407

ABSTRACT:

FIELD OF THE INVENTION
The field of invention relates to signal processing generally; and, more specifically, to a method and apparatus for a level shifter with a symmetrical output waveform.
BACKGROUND
FIG. 1
a
shows an embodiment of a differential to single ended level shifter
101
. A level shifter
101
changes an electronic signal's voltage level(s). Differential to single ended means the input signal is differential and the output signal is single ended.
FIG. 1
b
shows an embodiment of a transistor level design for the level shifter
101
of
FIG. 1
a
.
FIG. 1
c
shows an exemplary differential input signal (IN+, IN−)
102
c
,
103
c
and an exemplary single ended output signal (LS OUT)
104
c
for the level shifter embodiment
101
of
FIG. 1
b.
As observed with respect to the exemplary waveforms of
FIG. 1
c
, the level shifter
101
output signal
104
c
provides the same logical information as the differential input signal
102
c
,
103
c
(IN+, IN−) but with different voltage levels. That is, the input signals
102
c
and
103
c
(IN+ and IN−) swing over a voltage range of “A” volts while the output signal
104
c
(LS OUT), in response, swings over a voltage range of “Vcc” volts−where Vcc>A (noting that GND corresponds to 0.0 volts).
Different voltage swings (as between the input and output signals) correspond to the changing or “shifting” of at least one input voltage level to a new output voltage level. The particular level shifter
101
that is shown in
FIGS. 1
a
and
1
b
(and whose operation is demonstrated in
FIG. 1
c
) may be referred to as a “rail-to-rail” level shifter because the output signal
104
c
(LS OUT) swings between the shifter's supply rails of Vcc and GND. Rail-to-rail level shifters are often used for changing the levels of an electronic signal to better conform to those expected by digital circuitry (e.g., that is coupled to output
104
a,b
).
A problem with differential to single ended level shifters (including those of the rail-to-rail type) is the lack of symmetry between the rise times and fall times of the output signal waveform
104
c
(LS OUT). For example, referring to the exemplary output signal waveform
104
c
of
FIG. 1
c
, note that the signal rise time T
1
is less than the signal fall time T
2
. The asymmetry between rise and fall times arises from the asymmetry in the design of the level shifter.
That is, the conversion of a differential signal into a single ended signal involves asymmetrical processing. For example, referring to the exemplary transistor level embodiment of
FIG. 1
b
and the exemplary waveforms
102
c
,
103
c
and
104
c
of
FIG. 1
c
, note that a logic low IN−
103
c
signal value corresponds to logic high LS OUT
104
c
signal value of Vcc. According to the design of
FIG. 1
b
, the above described relationship between IN− and LS OUT is achieved by transistor Q
2
. Specifically, when IN− is a logic low Q
2
turns “on” which, in turn, effectively shorts the output node
104
b
to the Vcc rail.
Note also that a logic low IN+
102
c
signal value corresponds to a logic low LS OUT
104
c
signal value. According to the design of
FIG. 1
b
, the above described relationship between IN+ and LS OUT is achieved by transistors Q
1
, Q
3
and Q
4
. Specifically, when IN+ is a logic low Q
1
turns “on” which results in the driving of current through Q
3
. The driving of current through Q
3
raises the drain-to-source voltage across Q
3
which, correspondingly, also raises the gate voltage on Q
4
. Raising the gate voltage on Q
4
eventually turns “on” Q
4
which, in turn, effectively shorts the output node
104
b
to the GND rail.
Comparing the dynamics of how the output voltage rails of Vcc or GND are formed at the level shifter output node
104
b
, note that one transistor (Q
2
) is mostly involved with the raising of the output
104
b
LS OUT voltage to Vcc; while three transistors (Q
1
, Q
3
, Q
4
) are mostly involved with the lowering of the output
104
LS OUT voltage to GND. Because less transistors are involved with the raising of the output
104
b
LS OUT voltage than its lowering, the output
104
b
LS OUT voltage rises faster than it falls.
Hence, as mentioned above, the rise time T
1
of the output signal waveform
104
c
LS OUT (of
FIG. 1
c
) is less than its fall time T
2
. Problems may arise if a signal having an asymmetry (such as the level shifter output signal
104
c
LS OUT having the aforementioned difference between its rise and fall times) is processed or otherwise used. For example, data may be incorrectly interpreted.


REFERENCES:
patent: 5113097 (1992-05-01), Lee
patent: 5896045 (1999-04-01), Siegel et al.
patent: 6072333 (2000-06-01), Tsukagoshi et al.

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