Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-11-20
2003-12-16
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S690000, C257S686000, C257S787000
Reexamination Certificate
active
06664615
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit (IC) packages. More particularly, the invention relates to metal substrate IC packages use metal lead frames.
BACKGROUND OF THE INVENTION
The present invention combines the advantages of two types of IC packages: the Leadless Lead-frame Package (LLP) and the Ball Grid Array (BGA) package. A description of these two types of packages is presented here to better understand the object and advantages of their combination.
A LLP is a surface mounted IC package that uses a metal, usually copper lead-frame substrate to form the IC package. As illustrated in
FIG. 1
a
and the successively more detailed
FIGS. 1
b
and
1
c
, in known LLPs, a copper lead-frame strip or panel
101
is patterned, usually by stamping or etching, to define a plurality of arrays
103
of chip substrates
105
. Current LLP lead-frames are formed from metal sheets that are 8 mil thick. Each chip substrate
105
includes a die attach pad
107
and a plurality of contacts
109
disposed about associated die attach pad
107
. Very fine tie bars
111
are used to support die attach pads
107
and contacts
109
during manufacturing.
During assembly, IC dice are attached to respective die attach pads
107
and conventional wire bonding is used to electrically couple bond pads on each die to associated contacts
109
on chip substrate
105
. After the wire bonding, a plastic cap is molded over the top surface of each die and chip substrate
105
in array
103
. The capped dice are then cut from the array and individually tested using known sawing and testing techniques.
FIG. 2
shows a cross-section of a known LLP. The die attach pad
107
supports die
120
, usually attached by an adhesive
160
. Die
120
is electrically connected to its associated contacts
109
by bonding wires
122
. A molded plastic cap
125
encapsulates the die
120
and bonding wires
122
and fills the gaps between the die attach pad
107
and the contacts
109
thereby holding the contacts in place. During singulation, tie bars
111
are cut. The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using known techniques.
To produce an LLP with a large number of contacts, LLP designers usually arrange the contacts in multiple rows on each side of the die. The maximum wire bonding distance and desired final package size determine the maximum number of rows of contacts that can be formed.
Unlike an LLP that wire bonds directly from the die to the contacts, other known methods instead pattern the lead frame with leads, as shown FIG.
3
. In this configuration, patterned leads
5
form a radial pattern extending away from the die. Die
1
is wire bonded to leads
5
by bonding wires
2
such that they do not cross any other leads prior to bonding. Although it is very cost effective, this configuration has the disadvantages of a finished package that is significantly larger than the die, and a relatively low contact distribution density.
The BGA package overcomes much of the contact density problem associated with high pin count lead-frame packages. The principle difference between BGA style packages and lead-frame style packages is that BGA style packages have a laminated substrate, similar to a PCB, instead of a patterned metal plate as used for lead-frames. Laminated substrates are further distinguishable from patterned lead-frame by their IC package contacts located below the die mounting area.
The BGA package is formed by using an array of interconnecting contacts made up of solder balls or solder columns between the IC of the package and other electrical components external to the package such as a PC board. Flip chip ICs and BGA packages are two common examples of packages that use these arrays of interconnecting contacts.
BGA and fine pitch BGA substrates are commonly used in semiconductor packages. Referring to
FIGS. 4
a
and
4
b
, a semiconductor package utilizing a BGA substrate typically includes a semiconductor die
10
attached to a substrate
20
. Die
10
usually includes a plurality of die bond pads
50
. Substrate
20
typically includes a number of substrate pads
38
on the top surface of the substrate and a plurality of contacts
42
on the bottom surface of the substrate. Each substrate pad is typically electrically coupled to an associated contact
42
by way of traces
39
on the top and bottom surface of the substrate and associated vias
45
that electrically couple the top and bottom traces. The vias
45
typically have associated upper and lower via pads
40
and
41
to facilitate electrically coupling the vias to their associated traces
39
. The substrate pads
38
, traces
39
and via pads
40
and
41
are typically plated as a single layer on either surface of the substrate. Substrate pads
38
are typically positioned as close to die
10
as practically possible to minimize the length of bonding wires
30
necessary to couple die bond pads
50
to substrate pads
38
. Thus, the pitch of the substrate pads (i.e. the distance between the centers of adjacent substrate pads) tends to be quite fine to accommodate a relatively large number of bond pads
50
on the die. In contrast, vias
45
and via pads
40
and
41
are typically placed towards the periphery of substrate
20
since processing technology requires that they be spaced further apart than the substrate pads.
After die
10
has been properly attached and electrically coupled to substrate
20
, the upper surface of BGA substrate
20
is often encapsulated by an encapsulating material
55
. The finished semiconductor package
58
is usually cured to harden the encapsulating material
55
. Typically, solder balls are formed on contacts
42
, although other types of mounting contacts can be formed. When the semiconductor package
58
is attached to a printed circuit board
70
, the solder balls
60
are reflowed to electrically and physically couple semiconductor package
58
to pads
75
on printed circuit board
70
. Laminated substrates
20
are relatively thick as compared to lead-frames.
One problem with standard BGA packages is that substrate
20
is typically custom made to fit the specific requirements of a particular die. The die sizes, the die shapes, the number of I/O terminals (bond pads) per die as well as the bond pad pitch will often vary significantly for different devices, thus driving a requirement for custom substrate designs. A serious problem with BGA substrates is the amount of time required to manufacture them. Although the cycle time for dies has dramatically decreased, so that a die can now be manufactured within days, cycle times for manufacturing BGA substrates may be significantly longer. Generally, much of the delay in the production of BGA substrates is due to the intricate placement and routing of substrate input/output pads
38
, via pads
40
and
41
and contacts
42
.
BGA substrates also need custom tool testing equipment to handle each new BGA substrate. As custom BGA substrates typically have different footprints, and vary in size and pitch, testing equipment must be reconfigured for each semiconductor device. This results in increased cost and logistical problems for BGA IC device makers. Typically, the BGA substrate accounts for about 50 percent of the total BGA IC device cost.
The BGA package has the advantage over the LLP of a higher contact density. This translates to a smaller printed circuit board (PCB) footprint for an IC package with a given number of contacts. One reason for this is that the BGA has a much higher routing density and locates contacts below the die area, whereas the LLP must directly wire bond to peripheral contacts located beyond the boundaries of the die attachment plate. BGAs can scale up to much higher contact counts by using high density traces routed in the BGA substrate, overcoming much of the bonding density and distance limitations experienced by LLPs. Moreover, the longer bond wires required in LLP multi row contact arrangements introduce significantly
Bayan Jaime
Poddar Anindya
Flynn Nathan J.
Greene Pershelle
National Semiconductor Corporation
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