Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-08-29
2004-07-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C327S175000
Reexamination Certificate
active
06768697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates generally to the field of integrated circuit design and, more specifically, to producing more precise integrated circuit control signals.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Computer systems and other electronic devices typically include a variety of electrically interconnected integrated circuit (IC) packages which perform a variety of functions, including memory and processing functions. Integrated circuits, including memory devices, employ a variety of control signals to facilitate their operation. Examples of these control signals include clock, clock enable, address, data and the like. As integrated circuits continue to be designed for faster operation, the need for the control signals to be more precise becomes increasingly important. This is true because faster operational speeds are only possible by reducing the margin for error in the operation of the integrated circuit.
As an example, many types of integrated circuits have specifications for minimum setup and hold times. These specifications relate to the amount of time that is allowable for various operating conditions, such as the application or stabilization of an input signal. Setup and hold times may be required for certain signals before a new operation, such as a data read or data write, may occur. The setup and hold times for a given integrated circuit component are typically the shortest time for which correct operation of the device can be ensured. In other words, if an integrated circuit device is operated with setup and hold times that are shorter than the specified minimum setup and hold times, the device may not operate properly. Integrated circuits can be designed for faster operation only if minimum timing requirements such as setup and hold times can be made shorter.
Another important control signal for integrated circuit operation is the clock signal. Clock signals provide the “heartbeat” for the operation of many integrated circuits. Many timing and control operations, such as the strobing in of data and the like, are synchronized with the clock cycle. In many electronic systems, a single system clock will be provided to many different integrated circuit components (chips) so that all of the integrated circuits may operate based on a single clock signal. This type of system may be referred to as a synchronous system.
In a synchronous system, the precision and integrity of the clock signal is extremely important. Slight variations in the clock signal may adversely affect the operation of one or more integrated circuits. Also, there are many design challenges in providing an exact, precise clock signal to all integrated circuits in a given system. One problem that is commonly encountered is duty cycle skew.
An ideal clock signal is typically a perfect square wave with a 50% duty cycle. This means that the clock is at a logical high (“1”) level for exactly 50% of the time and at a logical low (“0”) level for exactly 50% of the time. Physical characteristics of a circuit board such as trace length or imprecision in the creation of the transitions between the logical high state and the logical low state (or vice versa) may contribute to a clock having a skewed duty cycle. An example of a clock with a skewed duty cycle is a clock that remains high for 51% of the time while remaining low for only 49% of the time. This skew may adversely impact the performance of some integrated circuits that use the skewed clock signal for synchronization.
Presently known clock skew correction circuits may employ a delay line to slightly delay a clock signal before it is delivered to another device. A multiplexer may be used to provide a more precise clock signal. In such an arrangement, the multiplexer may receive as inputs an original clock signal and the delayed clock signal, which is produced by passing the original clock signal through the delay line. The output of the multiplexer may be used as a clock signal to be delivered to another device. The selection of multiplexer input (the original clock signal or the delayed clock signal) may be controlled by a control signal. The control signal may select either the original clock signal or the delayed clock signal to provide as the output of the multiplexer, depending on which input signal will cause the output signal of the multiplexer to have a more precise duty cycle. For example, if the time in which the original clock signal is low accounts for only 49% of the period of the clock signal, the control line may select the delayed output when the original clock signal goes low to increase the time the clock outputs a logical low. In this manner, the duty cycle of the clock output of the multiplexer may be corrected to be more precise.
One factor that contributes to duty cycle skew, however, is device latency. Many integrated circuits, including dynamic random access memories (DRAMs), may have internal latency signals to provide synchronization for data output from the DRAM. The latency of the device is generally the amount of time it takes for the device to produce valid output data upon receiving a read request. Latency of a DRAM may be specified in clock cycles, such as two (2) clock cycles or one and one-half (1½) clock cycles.
The latency for a given device may be selectable by a user during device initialization or operation. For example, the latency of a DRAM may be programmed using a load mode cycle. After the latency of the device is programmed, the internal latency signal may be used to synchronize events inside the device. Because of individual device and layout characteristics, latency signals may undesirably introduce error or skew into clock signals or other control signals that are dependent on the latency signal. A compounding problem is that skew may occur when certain latency periods are programmed, but not when other latency periods are employed. A clock skew correction circuit that takes into account device latency is desirable.
REFERENCES:
patent: 5467041 (1995-11-01), Baba et al.
patent: 5550499 (1996-08-01), Eitrheim
patent: 5757218 (1998-05-01), Blum
patent: 6285226 (2001-09-01), Nguyen
patent: 6385129 (2002-05-01), Silvestri
Labrum Nick N.
Silvestri Paul A.
Fletcher Yoder
Mai Son
Micro)n Technology, Inc.
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