Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2005-09-27
2008-03-25
Li, Aimee J. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S214000
Reexamination Certificate
active
07350056
ABSTRACT:
An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a matrix of storage cells configured in rows and columns including a first row that couples to execution units. Instructions advance toward issuance from row to row as unoccupied storage cells appear. Unoccupied cells appear when instructions advance toward the first row and upon issuance. When a particular row includes an instruction that is not ready-to-issue a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row may bypass the row including the stalled or not-ready-to-issue instruction. Out-of-order issuance of instructions to the execution units thus continues.
REFERENCES:
patent: 3810118 (1974-05-01), Kiffmeyer
patent: 4056847 (1977-11-01), Marcantonio et al.
patent: 4799154 (1989-01-01), Matthews et al.
patent: 4837678 (1989-06-01), Culler et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5745726 (1998-04-01), Shebanow et al.
patent: 5941983 (1999-08-01), Gupta et al.
patent: 5944811 (1999-08-01), Motomura
patent: 5958043 (1999-09-01), Motomura
patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6289437 (2001-09-01), Eisen et al.
patent: 6351802 (2002-02-01), Sheaffer
patent: 6453407 (2002-09-01), Lavi et al.
patent: 6484253 (2002-11-01), Matsuo et al.
patent: 6587914 (2003-07-01), Campardo
patent: 6654869 (2003-11-01), Kahle et al.
patent: 6658551 (2003-12-01), Berenbaum et al.
patent: 6691221 (2004-02-01), Joshi et al.
patent: 6693814 (2004-02-01), McKenzie et al.
patent: 6704856 (2004-03-01), Farrell et al.
patent: 6725354 (2004-04-01), Kahle et al.
patent: 7028164 (2006-04-01), Jarvis et al.
patent: 2002/0007434 (2002-01-01), Campardo
patent: 2002/0087832 (2002-07-01), Jarvis et al.
patent: 2003/0120898 (2003-06-01), Fischer et al.
patent: 2004/0148493 (2004-07-01), Chu et al.
patent: 2005/0038979 (2005-02-01), Fischer et al.
Genua, “A Cache Primer”, Oct. 2004, Freescale Semiconductor.
Hartstein, et al., The Optimum Pipeline Depth for a Microprocessor, ISCA 2002.
Jones et al., “Software Directed Issue Queue Power Reduction”, HPCA 2005.
Nelson, “Priority Queues and the STL”, Dr. Dobb's Journal, Jan. 1996.
Wikipedia, “Out Of Order Execution”,downloaded from wikipedia.org on Jul. 1, 2005.
Rapaka et al., “A Mixed-Clock Issue Queue Design . . . ”, ACM, 2003.
Srinivasan, et al., “Formal Verification of an Intel XScale Processor Model . . . ” MEMCODE'03, Jun. 2003.
Koppanalil, et al., “A Case for Dynamic Pipeline Scaling”, ACM, 2002.
Tan, et al., “A Prioritized Cache for Multi-Tasking Real-Time Systems”, downloaded from ece.gatech.edu on Jul. 2, 2005.
Abernathy Christopher Michael
DeMent Jonathan James
Feiste Kurt Alan
Shippy David
Kahler Mark P
Li Aimee J.
Rifai D'Ann
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