Method and apparatus for isolating faults in a logic circuit

Details Method and apparatus for isolating faults in a logic circuit Method and apparatus for isolating faults in a logic circuit

1978-04-13

1980-03-18

Atkinson, Charles E.

Excavating

324 73R, 371 25, G06F 1100, G01R 3128

Patent

active

041941136

ABSTRACT:
A portable processor-oriented digital tester and method for isolating faults in digital printed circuit boards under test. The digital tester includes a processor, a main memory and a plurality of driver/sensor circuits. The main memory stores a signature file containing known correct signatures for the nodes of a board under test and also stores an image file which contains information defining the topology of the board under test. The driver/sensor circuits are programmable to receive test information generated by a test program stored in the main memory, transmit such information to inputs of a board under test, and receive information produced by the board under test in response to the input test information. The response received from outputs of the board under test is compared to a corresponding known-correct response to identify a faulty output of the board under test. The processor refers to the image file to identify a logic element driving the faulty output and to identify the nodes which are inputs to the logic element. The processor causes instructions to be displayed to the operator of the portable digital tester to instruct the operator to probe the input nodes of the logic element. A signature is generated for each node and compared to a corresponding known correct signature for that node as it is probed by the operator to identify a faulty input node. For each faulty node found, the measured signature, the initial state, and a number equal to the smaller of an input test number of the known correct initial transition of the faulty node and an input test number of the first incorrect transition of the faulty node is stored in a history file having pointers to the image file for each node. If a component is found having a faulty output and all good inputs, that component is identified as defective. If a loop is identified by the main processor, the operator is instructed to test all external inputs to the loop; if a faulty external input is found, the loop is resolved, and the processor instructs the operator to probe another node. If the external inputs are all good, the main processor scans the history table to determine which node in the loop failed first and indicates that the component driving that node is the probable fault.

REFERENCES:
patent: 3931506 (1976-01-01), Borrelli et al.
patent: 3976864 (1976-08-01), Gordon et al.
patent: 4097797 (1978-06-01), Finet
patent: 4108358 (1978-08-01), Niemaszyk et al.
patent: 4125763 (1978-11-01), Drabing et al.

Affiliated with

Also associated with

Rating

Method and apparatus for isolating faults in a logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for isolating faults in a logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for isolating faults in a logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1125259