Method and apparatus for isolating faults in a digital logic cir

Details Method and apparatus for isolating faults in a digital logic cir Method and apparatus for isolating faults in a digital logic cir

1986-09-02

1988-02-23

Fleming, Michael R.

Excavating

371 25, 364578, G06F 1100

Patent

active

047275456

ABSTRACT:
The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation generation program which provides a data base containing a list of possible faulty components for each cycle of the computer's clock for execution by a service processor of the actual computer during testing. The fault isolation generation program is generated by using a simulator loaded with a mathematical model of the actual computer in connection with the execution of the diagnostic program executed on the actual computer during testing. The fault isolation program generates a list of circuit elements capable of generating fault indications, excluding circuit elements not capable of generating such fault indications.

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