Method and apparatus for interruption processing in multi-proces

Details Method and apparatus for interruption processing in multi-proces Method and apparatus for interruption processing in multi-proces

1989-09-18

1994-03-22

Lee, Thomas C.

Boots, shoes, and leggings

395275, 395325, 364DIG1, 3642401, 3642412, 3642426, G06F 1314, G06F 13368

Patent

active

052972909

ABSTRACT:
An interruption signal from a common input/output device is coupled to all processors through a common bus, and each processor issues to the common bus its own interruption receipt acceptance or negation state and the respective processors watch and decide individually interruption receipt acceptance or negation states on the common bus of the individual processors. Only one of processors which are ready to accept the receipt of interruption is allowed to accept the receipt of an interruption signal from the common input/output device in accordance with a predetermined priority.

REFERENCES:
patent: 4499538 (1985-02-01), Finger et al.
patent: 4833598 (1989-05-01), Imamura et al.
patent: 4920486 (1990-04-01), Nielsen

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