Method and apparatus for interrupting a processor by a PCI perip

Details Method and apparatus for interrupting a processor by a PCI perip Method and apparatus for interrupting a processor by a PCI perip

1996-03-21

1998-06-23

Sheikh, Ayaz R.

395306, 395309, G06F 946

Patent

active

057713871

ABSTRACT:
A number of remote I/O ICUs, enhanced PCI--PCI bridges, and an ICC bus interface unit are distributively provided to a computer system having a processor and an hierarchy of PCI buses for facilitating PCI agents coupled to the lower level PCI buses to interrupt the processor during operation. The remote I/O ICUs, the enhanced functions of the PCI--PCI bridges, and the ICC bus interface unit advantageously leverage the PCI--PCI bridges' conventional ability in handling PCI type 1 configuration write transactions, to facilitate interrupt delivery and end of interrupt notification, by employing two specially defined PCI type 1 configuration write transactions, one for interrupt messages and another for end-of-interrupt (EOI) messages.

REFERENCES:
patent: 5499346 (1996-03-01), Amini et al.
patent: 5548730 (1996-08-01), Young et al.
patent: 5568619 (1996-10-01), Blackledge et al.
patent: 5594882 (1997-01-01), Bell
patent: 5619706 (1997-04-01), Young
PCI Local Bus Specification, Revision 2.1, PCI Special Interest Group, pp. 8-13, 81-97, Jun. 1, 1995.

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