Method and apparatus for interrupt/SMI# ordering

Details Method and apparatus for interrupt/SMI# ordering Method and apparatus for interrupt/SMI# ordering

1994-12-01

1996-08-27

Harvey, Jack B.

395733, 395735, G06F 1300

Patent

active

055510442

ABSTRACT:
A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.

REFERENCES:
patent: 4099255 (1978-07-01), Stanley et al.
patent: 4639549 (1987-01-01), Hirayama et al.
patent: 5386552 (1995-01-01), Garney

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