Method and apparatus for interim assembly electrical testing...

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

Reexamination Certificate

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Details

C324S715000, C438S012000

Reexamination Certificate

active

06552529

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is directed to electronic packaging and, more particularly, is directed to a method and apparatus for the interim testing of high temperature attach devices prior to the permanent attachment of low temperature attach devices on the same circuit board.
Solder reflow technology involves the use of solder reflow to make permanent, low resistance connections to produce a metallic contact of moderate strength. This technique requires that the bonded surfaces be subjected to high temperatures. A solder bond is a permanent bond and reworking a circuit board assembly to remove and replace a defective device subjects the entire assembly to elevated temperatures.
A circuit board typically contains contact pads that align with the contact pads on the device to be joined. Solder balls or solder bumps, typically a lead tin alloy, may be formed on either the device contact pads, the circuit board contact pads, or both. Alternatively, solder pastes may also be used. The surface mount device is then placed on the circuit board and the entire assembly is heated until the solder balls flow and form a good electrical connection between the contact pads. The array of solder balls thus serve as an interconnect mechanism between the contact pads on the device and the contact pads on the circuit board.
During the assembly of surface mount devices onto circuit boards such as ceramic or organic substrates, some devices may need assembly with different solder attach techniques and temperatures. If a high temperature attach device is not testable until a lower temperature attach device is mounted on the circuit board, and the high temperature attach device is found to be defective, all the low temperature attach devices must be removed before the defective high temperature attach device can be removed and replaced.
Ideal assembly processing would be to have all the devices joined at one temperature and through one common elevated temperature cycle. In this situation if a device requires replacement all the devices can sustain the temperature needed to remove the defective devices. Problems arise when devices attached at different temperatures are joined and the high temperature attach devices are found to be defective after circuit board electrical testing. Typically all the low temperature attach devices are removed, the high temperature attach devices are replaced and all the low temperature attach devices are joined again. It is necessary to remove the low temperature join devices because they cannot withstand the high temperature required to reflow the high temperature join devices. This can be very expensive and result in long rework cycles and the waste of good devices. If the circuit board could be tested early with only the high temperature attach devices joined, then any high temperature attach devices found defective could be reworked using conventional means before joining the low temperature attach devices. However, some circuit board testing requires the low temperature attach devices to also be present for electrical continuity or circuit tuning and thus need to be electrically connected in their respective positions on the circuit board.
There are a number of solutions proposed by others for electrically interconnecting circuit components. Difrancesco U.S. Pat. No. 5,506,514, the disclosure of which is incorporated by reference herein, describes a method and apparatus for electrically interconnecting circuit components, assemblies and subassemblies. Included are electronic components mounted on probe assemblies. The electronic components are on the opposite surface of the probe assembly from the substrate being tested and are connected by a wire. This does not provide the critical simulation of the device contact pad, RF field effects and other electrical interactions that will actually be present when the device is soldered onto the substrate.
Patel et al., U.S. Pat. No. 5,929,646, the disclosure of which is incorporated by reference herein, describes an apparatus and method to facilitate the testing of semiconductor devices packaged in surface mount modules while the module is connected to a circuit board. This is accomplished using an interposer mechanism that includes a top array of interposer contact pads and a bottom array of interposer contact pads. The reference does not provide for testing partially assembled modules.
Notwithstanding the prior art there remains a need for the direct test of a partially assembled circuit board when only high temperature devices are attached. Accordingly, it is a purpose of the present invention to provide a method and structure that allows the high temperature attach devices to be tested while on the circuit board before the low temperature attach devices are permanently joined thereby minimizing the time and cost of isolating defective high temperature attach devices.
It is another purpose of the present invention to provide a method and structure to allow the placement of low temperature attach devices which simulate the actual low temperature attach devices to be placed onto the circuit board being tested without permanently attaching the low temperature devices to the circuit board.
It is another purpose of the present invention to provide a test interposer which is used to test the circuit board in interim stages of device assembly such that these devices can be evaluated before committing them to solder attachment to the substrate.
These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.
BRIEF SUMMARY OF THE INVENTION
The purposes and advantages of the present invention have been achieved by providing, according to a first aspect of the invention a method for assembling a circuit board whereby high temperature attach devices can be electrically tested prior to the joining of permanent low temperature attach devices, the method comprising the steps of:
(a) joining at least one high temperature attach device onto a circuit board;
(b) placing a test interposer with a least one low temperature known good reference device mounted on the test interposer in electrical contact with the circuit board and at least one high temperature attach device;
(c) testing the high temperature attach devices while they are in electrical contact with the low temperature known good reference devices in order to identify any defective high temperature attach devices;
(d) removing the test interposer from the circuit board;
(e) performing the following steps only if a defective high temperature attach device is present:
(i) removing any defective high temperature attach devices if any are present, from the circuit board;
(ii) joining additional high temperature attach devices to replace any defective high temperature attach devices, if any are present;
(iii) placing the test interposer with the low temperature known good reference devices mounted on the test interposer in electrical contact with the circuit board;
(iv) retesting the high temperature attach devices while they are in electrical contact with the low temperature known good reference devices to identify defective high temperature attach devices;
(v) removing the test interposer from the circuit board; and
(vi) repeating steps (i) to (v) until no defective high temperature attach devices are present; and
(f) joining the permanent low temperature attach devices on the circuit board to complete the circuit board assembly.
According to another aspect of the invention, there is provided a structure for electrically testing the high temperature attach devices on a circuit board prior to the joining of the permanent low temperature attach devices, comprising:
a circuit board;
at least one high temperature attach device joined on the circuit board;
a test interposer;
cutout areas in the test interposer corresponding to the size and location of the high temperature attach devices on the circuit board; and
at least one low temperature known good

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