Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Reexamination Certificate
1999-07-16
2003-07-15
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
C375S220000, C375S354000
Reexamination Certificate
active
06594327
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to network interface communication. Specifically, this invention is directed towards a method and apparatus for interfacing to E1 or T1 networks.
BACKGROUND
Currently, there are many specifications for the transmission of serial data streams. However, there are two predominant standards that are in use. The first, used in such areas as North America, is DS1. The second, known as E1, is used mainly in European countries.
DS1, also known as T1, is a broadband standard for transmission of a serial data stream at 1.544 megabits per second (Mb/s). DS1, at the logical link layer, requires a specific method of framing the payload data. The framing is required for the demarcation of each frame to allow the extraction of the channelized traffic, payload, cyclic redundancy checking, and management information on the receiving end for appropriate processing. The framing structures are specified by the American National Standards Institute (ANSI) T1.403-1995, titled “Telecommunications—Network-to-Customer Installation—DS1 Metallic Interface”; International Telecommunication Union (ITU) G.704, titled “Synchronous frame structure used at 1544, 6312, 2048, 8448 and 44 736 kbit/s hierarchical levels”; and, ITU G.706, titled “Frame alignment and cyclic redundancy check (CRC) procedures relating to basic frame structures defined in Recommendation G.704”.
The framing structure for T1 requires that 1 overhead bit be inserted after every 192 bits of payload, such that one frame consists of 193 bits. The overhead bit identifies the frame boundary and may also be used for management functions. Thus, the overhead bit may be a framing bit, a cyclic redundancy check bit, or a link management bit. The overhead bit is inserted into the transmitted stream at the transmit side. On the receive side, the incoming bit stream is examined to find the overhead bit (e.g., framing boundary). Once the location of the framing boundary is found, payload and control information may be extracted. The process of finding the framing bit location in the absence of any errors should complete within 50 milliseconds.
A DS1 frame synchronizer located at the receive side is responsible for locating the overhead bit (e.g., the framing boundary) in an incoming data stream. Once the frame synchronizer has located the overhead bit, the payload and overhead portions may be extracted from the stream of data. In DS1, the data rate is specified to be at 1.544 Mb/sec. As minor deviations in the data rate are acceptable, the detected clocking of the incoming data is extracted at the receive side by the physical layer transceivers of the network device and sent to the DS1 frame synchronizer along with the data.
Another currently widely deployed standard is the E1, which is a European broadband standard for transmission of a serial data stream at 2.048 Mb/s. The E1 logical and physical layer requirements are also specified by the standards set forth in ITU G.704 and ITU G.706. Similar to DS1, the clocking of the incoming data is extracted at the receive side by the physical layer transceivers and sent to the E1 frame synchronizer along with the data. The E1 frame synchronizer has functions similar to the DS1 frame synchronizer, which is to analyze the stream of data presented by the physical layer and extract the payload and overhead data. However, the E1 standard provides that, instead of inserting 1 overhead bit after 192 payload bits in a frame as specified in DS1, 8 overhead bits are inserted at the beginning of every frame.
Currently, E1 and DS1 frame synchronizers are produced as application specific integrated circuits (ASICs). In addition, these ASICs are produced as different parts primarily due to the differences between the two standards. Thus, two different devices must currently be produced, one for each type of system. For each type of device, a different clocking signal must be used. Having to provide different devices that support different systems adds cost and complexity to the infrastructure of a company, in addition to added inventory and support costs.
SUMMARY
It is therefore an intended advantage of one of the described embodiments to provide an ASIC that may be configured to function as an E1 or T1 frame synchronizer.
It is a further intended advantage of the present invention to provide a single clocking interface for the ASIC, such that only one clock signal needs to be provided to the ASIC.
These and other intended advantages of the described embodiments are provided by an improved de-framer that may operate with data streams generated by various input clocks. The de-framer includes a frame buffer memory; a set of frame synchronizers coupled to the frame buffer memory; and, a set of receivers coupled to the buffer memory and a corresponding frame synchronizer in the set of frame synchronizers. Each receiver is configured to receive a data stream at a first clock rate, and detect changes in the data stream at a second clock rate.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5615237 (1997-03-01), Chang et al.
patent: 5956377 (1999-09-01), Lang
patent: 5974104 (1999-10-01), Dhara
Daniel Minoli, Enterprise Networking: Fractional T1 to SONET, Frame Relay to BISDN, pp. 95-110, Library of Congress Cataloging-in-Publication Data, 1993 Artech House, Inc.Norwood MA.
Blakely , Sokoloff, Taylor & Zafman LLP
Chin Stephen
Fan Chieh M.
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