Multiplex communications – Wide area network – Packet switching
Patent
1989-02-03
1990-10-23
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 859, H04J 324
Patent
active
049657933
ABSTRACT:
To interface a system control unit with an input/unit in a computer system, an interface includes a transmitter for sequentially transmitting data packets and parity signals between the system control unit and the input/output unit, and a receiver for sequentially receiving the data packets and parity signals. The receiver includes a buffer for storing a plurality of the data packets. The stored data packets are controllably unloaded from the buffer, and a buffer emptied signal is sent back to the transmitter as each data packet is unloaded. The transmitter has a counter which calculates the number of data packets stored in the buffer and asserts a signal that prevents the transmitter from transmitting additional data packets when the buffer becomes full. The receiver compares the parity of the received data packets to the respective parity signals to check for parity errors. The receiver sends an acknowledge signal back to the transmitter in the absence of a parity error, and sends a retry signal back to the transmitter in the presence of a parity error. Preferably the data packets are transmitted along with a separate transmitter clock signal and respective command available signals, and the returned signals are sent back to the transmitter with a separate receiver clock signal, to permit synchronous reception of the data packets or returned signals. Respective data synchronizers in the transmitter and receiver eliminate the effect of skew between the transmitter and receiver clock signals.
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Fossum et al., "An Overview of the VAX 8600 System," Digital Technical Journal, No. 1, Aug. 1985, pp. 8-23.
Lin Rueysen
Niles Roger G.
Polzin R. Stephen
Digital Equipment Corporation
Hsu Alpus H.
Olms Douglas W.
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