Method and apparatus for integrating capacitors in stacked...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S774000

Reexamination Certificate

active

07605458

ABSTRACT:
Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

REFERENCES:
patent: 5825080 (1998-10-01), Imaoka et al.
patent: 7068072 (2006-06-01), New et al.
patent: 7193239 (2007-03-01), Leedy
patent: 7355273 (2008-04-01), Jackson et al.
patent: WO 02/17367 (2002-02-01), None
Ryu et al., High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging, Sep. 2006, Electronics Systemintegration Technology Conference 2006, pp. 215-220.
Rahman, Arifur et al., “Die Stacking Technology for Terabit Chip-to-Chip Communications”, Sep. 1, 2006, pp. 587-590, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Kuhn, Stefan A., et al., “Interconnect Capacitances Crosstalk, and Signal Delay in Vertically Integrated Circuits”, 1995, 4 pages, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Bollmann, D., “Three Dimensional Metallization for Veritcally Integrated Circuits”, Materials for Advanced Metallization, 1997, pp. 94-98, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Ieong, Meikei, et al., “Three Dimensional CMOS Devices and Integrated Circuits”, 2003, pp. 207-213, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Guarini, K.W., et al., “Electrical Integrity of State-of-the-Art 0.13 um SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication”, 2002, pp. 943-945, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Baliga, John, “Through-Silicon Technology, Applications Growing”, Semiconductor International, Mar. 1, 2005, 3 pages, available from Reed Business Information @ http://www.reed-electronics.com?semiconductor/index/asp?layout=articlePrint&articleID=CA507186.
Garrou, Philip, “Future ICs Go Vertical”, Semiconductor International, Feb. 1, 2005, 9 pages, available from http://www.reed-electronics.com?semiconductor/index/asp?layout=articlePrint&articlelD=CA499680.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for integrating capacitors in stacked... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for integrating capacitors in stacked..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for integrating capacitors in stacked... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4084372

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.