Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-06-28
2011-06-28
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C257S686000
Reexamination Certificate
active
07968375
ABSTRACT:
Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.
REFERENCES:
patent: 5825080 (1998-10-01), Imaoka et al.
patent: 6524926 (2003-02-01), Allman et al.
patent: 7068072 (2006-06-01), New et al.
patent: 7193239 (2007-03-01), Leedy
patent: 7355273 (2008-04-01), Jackson et al.
patent: 2005/0186705 (2005-08-01), Jackson et al.
patent: WO 02/17367 (2002-02-01), None
patent: WO 0217367 (2002-02-01), None
U.S. Appl. No. 12/503,429, filed Jul. 15, 2009, Rahman et al.
U.S. Appl. No. 11/701,807, filed Feb. 1, 2007, Rahman et al.
Baliga, John, “Through-Silicon Technology Applications Growing,”Semiconductor International, Mar. 1, 2005, pp. 1-3, Reed Business Information, New York, New York, USA.
Bollmann, D., “Three Dimensional Metallization for Vertically Integrated Circuits,”Proc. of the 1997 European Workshop on Materials for Advanced Metallization, Mar. 16, 1997, pp. 94-98, IEEE, Piscataway, New Jersey, USA.
Garrou, Philip, “Future ICs Go Vertical,”Semiconductor International, Feb. 1, 2005, pp. 1-9, Reed Business Information, New York, New York, USA.
Guarini, K.W. et al., “Electrical Integrity of State-of-the-Art 0.13 μm SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication,”International Electron Devices Meeting Digest, Dec. 8, 2002, pp. 943-945, IEEE, Piscataway, New Jersey, USA.
Ieong, Meikei, “Three Dimensional CMOS Devices and Integrated Circuits,”Proc. of the IEEE 2003 Custom Integrated Circuits Conference, Sep. 21, 2003, pp. 207-213, IEEE, Piscataway, New Jersey, USA.
Kuhn, Stefan A. et al., “Interconnect Capacitances, Crosstalk, and Signal Delay in Vertically Integrated Circuits,”Proc. of the International Electron Devices Meeting, Dec. 10, 1995, pp. 249-252, IEEE, Piscataway, New Jersey, USA.
Rahman, Arifur, “Die Stacking Technology for Terabit Chip-to-Chip Communications,”Proc. of the 2006 IEEE Custom Integrated Circuits Conference, Sep. 10, 2006, pp. 587-590, IEEE, Piscataway, New Jersey, USA.
Ryu, Chunghyun et al., “High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging,”Proc. of the 2006 Electronics Systemintegration Technology Conference, Sep. 5, 2006, pp. 215-220, IEEE, Piscataway, New Jersey, USA.
Rahman Arifur
Trimberger Stephen M.
Brush Robert M.
Cartier Lois D.
Maunu LeRoy D.
Payen Marvin
Pham Thanh V
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