Method and apparatus for integrated undersampling

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system

Reexamination Certificate

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C702S072000, C702S180000, C702S189000, C324S076150

Reexamination Certificate

active

10930292

ABSTRACT:
An undersampling system can comprise an IC that has integrated, on the same physically contiguous IC, both an undersampler circuit and a receiver circuit whose input is to be monitored by undersampling. For a current phase of sample clocks relative to an input signal, the input signal is sampled until a sufficient number of samples are collected in a one dimensional histogram associated with the current phase. The phase of the sample clocks, relative to the input signal, can then be shifted. Such phase shift can be accomplished by a phase mixer. The phase shift can be small enough to provide sufficient resolution in a composite sampled image of the input signal. A mean value can be computed for each one dimensional histogram, resulting in a representation of the undersampled signal as a function of time that is suitable for further processing.

REFERENCES:
patent: 6191718 (2001-02-01), Matsumoto
patent: 6532441 (2003-03-01), Urso
patent: 6640193 (2003-10-01), Kuyel
Stewart, “Effect of sample clock jitter on IF-sampling IS-95 receivers”, Sep. 1-4, 1997, The 8th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 1997, vol. 2, pp. 366-370.
Kiyono et al., “Jitter effect on digital downconversion receiver with undersampling scheme”, Jul. 25-28, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004, IEEE, vol. 2, pp. II-677 to II-680.
“Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits.” Ron Ho, Bharadwaj Amrutur, Ken Mai, Bennett Wilburn, Toshihiko Mori, and Mark Horowitz. Symposium on VLSI Circuits, 1998, Digest of Technical Papers. Publication date: June 11-13, 1998. On pp. 138-139.

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