Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2006-02-28
2006-02-28
Khatri, Anil (Department: 2193)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S144000, C717S156000
Reexamination Certificate
active
07007271
ABSTRACT:
The present invention describes a method of efficiently optimizing instruction scheduling and register allocation in a post optimizer. The method removes false register dependencies between pipelined instructions by building an incremental (partial) interference graph of register allocation for scheduled instructions. False dependency graph indicates the amount of parallelism in the data flow graph. The incremental interference graph uses a mix of virtual and physical registers. The interference graph is built incrementally as an instruction schedular schedules each instruction. The optimization is done incrementally on localized code. The physical register mapping is maximized and virtual registers are created on demand basis.
REFERENCES:
patent: 5202975 (1993-04-01), Rasbold et al.
patent: 5230050 (1993-07-01), Iitsuka et al.
patent: 5606697 (1997-02-01), Ono
patent: 5613121 (1997-03-01), Blainey
patent: 5790874 (1998-08-01), Takano et al.
patent: 5937190 (1999-08-01), Gregory et al.
patent: 5999734 (1999-12-01), Willis et al.
patent: 6031994 (2000-02-01), Radigan
patent: 6059841 (2000-05-01), Caracuzzo
patent: 6263489 (2001-07-01), Olsen et al.
patent: 6374403 (2002-04-01), Darte et al.
patent: 6631514 (2003-10-01), Le
patent: 6651246 (2003-11-01), Archambault et al.
patent: 6675380 (2004-01-01), McKinsey et al.
patent: 6711728 (2004-03-01), Otsubo
patent: 6718541 (2004-04-01), Ostanevich et al.
patent: 6751792 (2004-06-01), Nair
Gupta et al, “Resource sensitive profile directed data flow analysis for code optimization”, IEEE, pp 358-368, 1997.
Ngassam et al, “Hardcoding finite state automata processing”, ACM SAICSIT, pp 111-121, 2003.
Jacobson et al, Achieving fast and exact hazard free logic minimization of extended burst mode gc finite state machine:, Proc. of IEEE/ACM Int. Conf. on CAD, pp 303-310, Nov. 2000.
Moon et al, “A study on the number of memory ports inmultiple instruction issues machines”, IEEE, pp 49-58, 1993.
Kumar Anoop
Nair Sreekumar Ramakrishnan
Khatri Anil
Sun Microsystems Inc.
Zagorin O'Brien Graham LLP
LandOfFree
Method and apparatus for integrated instruction scheduling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for integrated instruction scheduling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for integrated instruction scheduling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3707561