Method and apparatus for integrated circuit diagnosis

Details Method and apparatus for integrated circuit diagnosis Method and apparatus for integrated circuit diagnosis

1991-04-30

1994-06-28

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364578, G06F 1560

Patent

active

053253094

ABSTRACT:
A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A tester stimulates the a device (DUT) with input patterns. DUT output patterns are communicated back to the tester, and are compared to simulation results. Failing outputs are identified. Working back from the failing output, suspect failing nodes are identified in a schematic editor. Through a layout database linked to the schematic editor, the position of each suspect failing node is identified. A probe and SEM are positioned at nodes suspected of causing the failure. Live waveforms generated by the probe are compared with simulated waveforms for the node, while the DUT is being re-exercised by the tester. In a windowed display environment, the user is provided with schematic, layout, SEM image, and live and simulated waveforms for the suspect node. Node after node are explored in this manner until the failing circuit element is identified. Documentation is provided by printing any and all of the windows.

REFERENCES:
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4813013 (1989-03-01), Dunn
patent: 4833619 (1989-05-01), Shimizu et al.
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5034899 (1991-07-01), Schult
patent: 5111413 (1992-05-01), Lazansky et al.

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