Patent
1995-11-17
1998-11-10
Kriess, Kevin A.
G06F 944
Patent
active
058357769
ABSTRACT:
Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units. They also have the ability to add two values to form the address within memory load and store instructions. In such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduled loops. The invention consists of a technique to achieve this speed up by systematically reducing the number of certain overhead instructions in modulo scheduled loops. The technique involves identifying reducible overhead instructions, scheduling the balance of the instructions with normal modulo scheduling procedures and then judiciously inserting no more than three copies of the reducible instructions into the schedule.
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Baylin Boris
Subramanian Krishna
Tirumalai Partha P.
Basinski Erwin J.
Kriess Kevin A.
Sun Microsystems Inc.
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