Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-04-11
2004-09-07
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06788090
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and an apparatus for inspecting semiconductor devices such as semiconductor integrated circuits and semiconductor memory devices, and more particularly to an inspection method and an inspection apparatus for semiconductor devices by which an increased number of semiconductor devices can be inspected simultaneously.
2. Description of the Related Art
When a semiconductor device is inspected upon manufacture or delivery, usually a semiconductor tester and the semiconductor device to be inspected are connected to each other through a probe card or a test board. Then, a predetermined inspection signal is applied to each pad or each pin for an input signal of the semiconductor device under the inspection, and a signal at each pad or each pin for an output signal of the semiconductor device then is detected. A semiconductor device of the inspection object may be referred to also as DUT (Device Under Test).
In the field of semiconductor devices, a terminology is sometimes used in different manners depending upon whether a semiconductor device is not packaged as yet or is packaged already in such a manner that, for the semiconductor device before packaged, a representation “to connect to a pad with a probe card used” is used, but for the semiconductor device after packaged, another representation “to connect to a pin with a test board” is used. In the following description, however, pads and pins of semiconductor devices are generally referred to as terminals. Also the probe card for connecting a semiconductor device of the inspection object to a tester is used to include a test board.
In inspection of a semiconductor device, it is requested to minimize the inspection time. To this end, it has been attempted to inspect a plurality of semiconductor devices simultaneously.
FIG. 1
shows a basic configuration for inspecting a plurality of semiconductor devices simultaneously with a single tester used.
Tester
61
for inspecting semiconductor devices in accordance with a test program includes a plurality of drivers
62
each for applying a predetermined signal to a terminal
65
for an input signal of semiconductor device
64
to be inspected. Each of semiconductor devices
64
has a plurality of terminals
65
each for an input signal. Tester
61
and semiconductor devices
64
are connected to each other through probe card
63
. One driver
62
in tester
61
corresponds to one terminal
65
, and therefore, a number of drivers
62
greater than the total number of input terminals
65
of the semiconductor devices
64
to be inspected are prepared.
After all, in the configuration described above, a number of drivers equal to the total number of terminals for an input signal of semiconductor devices to be inspected simultaneously must be prepared in the tester. Therefore, the configuration described has a problem in that the tester has a large-scale configuration. Further, the number of the drivers that are provided in the tester limits the number of semiconductor devices that can be inspected simultaneously. Therefore, the configuration has another problem in that the number of simultaneously inspected semiconductor devices cannot be increased very much.
It is generally considered that semiconductor devices that are inspected simultaneously are of the same type. Thus, Japanese Patent Laid-Open No. 11-231022 (JP, 11231022, A) discloses an apparatus wherein a signal from a driver of a tester is branched in a probe card and supplied in parallel to a plurality of semiconductor devices to be inspected simultaneously as seen from
FIG. 2. A
wiring scheme by which a signal from a driver is branched and supplied in parallel to a plurality of semiconductor devices is called common drive wiring, and a driver used in such common drive wiring is called a common driver.
In the configuration shown in
FIG. 2
, three terminals
65
a
to
65
c
, and
65
d
to
65
f
for an input signal are respectively provided for each of a plurality of semiconductor devices
64
a
,
64
b
. The output of driver
62
a
from among the drivers in tester
61
is connected to terminal
65
a
of semiconductor device
64
a
, and the output of driver
62
d
is connected to terminal
65
d
of another semiconductor device
64
b
. However, the output of driver
62
b
is branched at branching point
66
a
in probe card
63
and supplied to terminal
65
e
of semiconductor device
64
b
. Similarly, the output of driver
62
c
is branched at branching point
66
b
in probe card
63
and supplied to terminal
65
c
of semiconductor device
64
a
and terminal
65
f
of semiconductor device
64
b
. Since the output of each of drivers
62
b
,
62
c
is branched and connected to a plurality of terminals for an input signal, drivers
62
b
,
62
c
are common drivers.
Such a configuration as described above includes a driver that takes charge of a plurality of terminals and therefore allows a greater number of semiconductor devices to be inspected with a small number of drivers used.
This configuration, however, has a problem in that, if one of semiconductor devices inspected simultaneously has a defect such as leak or a short-circuit at an input terminal, inspection of the remaining normal semiconductor devices is disabled. Where the input terminal of a semiconductor device to be inspected has a MOS (metal-oxide-semiconductor) transistor configuration or a CMOS (complementary MOS) configuration, it is considered that the input resistance of the input terminal is equal to or higher than 0.5 M&OHgr;, typically equal to or higher than approximately 3 M&OHgr;. Therefore, the drivers in a tester are so configured that the current driving capacity thereof may conform to the input resistance. Here, if leak of 100 &OHgr; or less when converted into an input resistance for dc, for example, occurs with one of a plurality of input terminals to which a signal branched from a driver is applied, then a normal signal voltage is not applied to the normal input terminals either. This disables inspection of a normal semiconductor device as well.
This is described in connection with the example shown in FIG.
2
. It is assumed here that semiconductor device
64
a
is a non-defective unit and semiconductor device
64
b
is a defective unit in that leak occurs with input terminal
65
e
thereof. Terminal
65
e
with which leak occurs and terminal
65
b
of semiconductor device
64
a
of a non-defective unit are connected in parallel to driver
62
b
. Therefore, when terminals
65
b
,
65
e
are driven by driver
62
b
, because of the leak at terminal
65
e
, a regular signal voltage is not applied to normal terminal
65
b
either, and also semiconductor device
64
a
of a non-defective unit cannot be inspected normally.
As a countermeasure to solve the problem described above where a signal from a driver is branched and applied to a plurality of input terminals, it is attempted to insert a resistor of approximately several hundreds ohms between a branching point and each input terminal after a signal from a driver is branched in a probe card as seen in FIG.
3
. The configuration shown in
FIG. 3
is a modification to the configuration shown in
FIG. 2
in that resistors
67
of approximately several hundreds ohms (600 &OHgr;, for example) are inserted between branching point
66
a
and terminal
65
b
, between branching point
66
a
and terminal
65
e
, between branching point
66
b
and terminal
65
c
, and between branching point
66
b
and terminal
65
f.
Although this configuration is effective for inspection of a semiconductor device whose clock frequency is comparatively low such as approximately 10 MHz or less, it cannot be used for inspection of a semiconductor device whose clock frequency is higher than 30 MHz. The reason is that, since the input capacitance of each input terminal of a semiconductor device to be inspected is typically 5 pF and provides a time constant of approximately 3 ns together with the inserted register (typically having a resi
Cuneo Kamand
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Nguyen Jimmy
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