Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Manufacturing optimizations
Reexamination Certificate
2010-03-24
2011-12-06
Memula, Suresh (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Manufacturing optimizations
C716S055000
Reexamination Certificate
active
08074187
ABSTRACT:
Some embodiments of the invention provide a method for inserting several fills in an integrated circuit (“IC”) layout. The method identifies a set of potential fills in a region of an IC layout, where the set of potential fills has a first fill size, wherein the first fill size is from a set of fill sizes. The method specifies a halo around each potential fill in the set of potential fills. For each potential fill, the method determines whether the specified halo overlaps with a foreign object in the region of the layout. For each potential fill, the method specifies a legal fill in the region of the IC layout if the specified halo does not overlap with a foreign object in the region of the IC layout. The method inserts at least one legal fill in the region of the IC layout. In some embodiments, the halo is a spacing halo.
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Ylinen Judd Matthew
Yue Kwok Ming
Adeli & Tollen LLP
Candence Design Systems, Inc.
Memula Suresh
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