Pulse or digital communications – Synchronizers
Reexamination Certificate
2000-04-28
2004-06-01
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Reexamination Certificate
active
06744834
ABSTRACT:
BACKGROUND OF THE INVENTION
Initializing a synchronizer that is used to synchronize data between clock domains running at the same frequency but with an unknown phase relationship poses several challenges. For example, a low latency synchronizer writes into a data latch in the transmitting clock domain yet reads data from the synchronizer in the receiving clock domain. Such a synchronizer has a relationship between its write pointer and its read pointer that can be maintained indefinitely once that relationship has been established. The problem is determining the relationship between the read and write pointer and initializing the synchronizer with the proper values.
Initialization becomes more complicated in a system with multiple bitsliced interfaces. For systems having multiple bitsliced interfaces, data received into different synchronizers on different chips must be read into the receiving chip(s)'s core clock domain(s) in lockstep with one another. The problem with receiving data in lockstep is that typically the multiple bitsliced interfaces have no communication with one another. This creates a problem since the particular edge of the receiving chip(s)'s clocks which clocks in the data must be one where the data will always be stable and valid. Thus, the synchronizer initialization process needs to account for the largest possible arrival range for the data that needs to be in lockstep without sacrificing too much latency.
There are two problems in particular that make synchronizer initialization difficult: (1) uncertain data arrival time and (2) uncertain data arrival location. Regarding uncertain data arrival time, for data on a particular trace, from any manufactured board or chip to another there may be large variations in the data arrival time at the synchronizer due to large clock skew numbers and process, voltage, temperature (PVT) variations, or bitsliced data may travel across different trace lengths from different chips. As a result, it might be unknown when all the data that needs to be in lockstep together will arrive relative to one another. In addition, the time required for the data to go from the sending chip to the receiving chip (1 cycle, 2 cycles, etc.) might also be unknown.
Regarding uncertain data arrival location, at reset clocks become valid at different times. Thus, the same data symbol from the transmitting chip may go into different data latches in each bitsliced interface. So not only is there no known, fixed time between when the data arrives at the receiving chip and the correct edge at which to latch it, but there is also no known fixed latch from which to latch it.
An initialization process and apparatus that addresses the described challenges, that synchronizes data in multiple bitsliced interfaces in lockstep with one another safely and with low latency, is needed.
SUMMARY OF THE INVENTION
An initialization process and apparatus that initializes a synchronizer that synchronizes data to multiple bitsliced interfaces in lockstep with one another safely and with low latency is provided. The initialization circuitry is used to initialize a synchronizer that synchronizes data between sending chip(s) to receiving chip(s). In the preferred embodiment, the initialization circuitry includes a pattern generator for generating an initialization pattern, a pattern detector for recognizing the initialization pattern, a write control circuit and a read select circuit. The initialization pattern is generated on the sending chip and is detected by the pattern detector circuit located on the receiving chip. The pattern detector is electrically coupled to the output of the pattern generator (latched in the data buffer of the synchronizer) so that it can detect the pattern sent across the link. The read select circuit is electrically coupled to the data buffer of the synchronizer. A predetermined number of cycles after receipt of a unique clock cycle identifier signal (the global frame clock) by the read select circuit, valid data in lockstep with other bitsliced interfaces can be read from a data buffer of the synchronizer.
The method for initializing the synchronizer includes the steps of: sending an initialization pattern to the pattern detect logic circuit; detecting the initialization pattern; responsive to detection of the initialization pattern, setting the write pointer to point to a predetermined location in the data buffer circuit (where the predetermined location is the first latch of the data buffer circuit); and responsive to detection of a unique clock cycle identifier signal, reading the data from the data buffer a predetermined number of cycles after recognition of the unique clock cycle identifier signal.
Part of the synchronizer initialization process (detecting a unique clock cycle identifier, and reading data in the first data latch a predetermined number of cycles after detection of the unique clock cycle identifier signal) is directed towards the critical timing of reading data from the sending chip. Data from the sending chip is buffered in the data buffer circuitry of the synchronizer of the receiving chip. Timing is critical since for multiple bitsliced interfaces, data from all of the interfaces must be read in lockstep. The combination of a unique clock cycle identifier (the global frame clock), and a predetermined delay (determined by the SYNC_CONFIG bits) helps define the critical timing relationship of the synchronizer. Once the timing is established upon synchronizer initialization, valid data can continue to be read by the receiving chip at the proper time.
In the preferred embodiment, the global frame clock (GFC) is used by the receiving chip as a unique clock cycle identifier to synchronize data across interfaces so that data can be read in lockstep. The GFC as a synchronizing signal is easy to create and route with low skew to the chip clocks, since it is preferably a low frequency clock signal that has the same skew as the core clock. The GFC marks a unique chip core clock cycle on each chip, thus allowing the synchronizer control logic to pull data from the different receiving chips in the system on the same clock edge.
The GFC is distributed to all of the receiving chips on the link so that none of the chips need to communicate directly. This allows synchronization of bitsliced data to be much faster than if communication between the chips had to take place. Because the GFC signal can be easily routed to multiple chips, the synchronizer design and initialization process and apparatus can easily be used with any number of bitsliced interfaces. Further, the GFC provides the additional advantage of saving chip real estate and/or pins. Because the GFC is known to be a synchronous signal, the bitsliced chips do not need additional logic to communicate with one another.
A predetermined number of cycles after recognition of the unique clock cycle identifier signal, the GFC, data is read from the first data latch in the synchronizer data buffer (a FIFO). The predetermined delay is related to the synchronizer configuration (SYNC_CONFIG) bits. The synchronizer configuration bits, in the preferred embodiment two bits, are determined prior to synchronizer initialization and are dependent on the worst case latency of the synchronizer.
Because the circuit configuration, length of wires, resistance of wires, number of circuit elements, and impedances associated with circuit elements is known, the worst case latency can be calculated. The worst case latency is assumed in order to ensure that valid data is read. The SYNC_CONFIG bits also allow adjustments to be made during lab link debug and characterization. After validation and testing in the lab, the final value for volume shipments can be set.
Having a configuration value, SYNC_CONFIG, is advantageous in several ways. It allows reading from the synchronizer FIFO at a time when the data is known through analysis to always be stable and valid for registering into the core clock domain. It is programmable, allowing testing and then reconfiguration later to a different lat
Hewlett--Packard Company
Vo Don N.
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