Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2008-12-08
2010-02-09
Mai, Son L (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S233140, C365S236000, C327S147000, C327S156000, C327S160000
Reexamination Certificate
active
07660187
ABSTRACT:
A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.
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Johnson James Brian
Keeth Brent
Lin Feng (Dan)
Johnson Matthew W.
Jones Day
Mai Son L
Micro)n Technology, Inc.
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