Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-06-20
2006-06-20
Mai, Son (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S236000
Reexamination Certificate
active
07065001
ABSTRACT:
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
REFERENCES:
patent: 5745421 (1998-04-01), Pham et al.
patent: 5825226 (1998-10-01), Ferraiolo et al.
patent: 5963502 (1999-10-01), Watanabe et al.
patent: 5999580 (1999-12-01), Sakoda et al.
patent: 6269051 (2001-07-01), Funaba et al.
patent: 6300807 (2001-10-01), Miyazaki et al.
patent: 6337589 (2002-01-01), Ooishi
patent: 6385126 (2002-05-01), Jung et al.
patent: 6400197 (2002-06-01), Lai et al.
patent: 6434684 (2002-08-01), Manning
patent: 6437618 (2002-08-01), Lee
patent: 6621762 (2003-09-01), Roohparvar
patent: 6687185 (2004-02-01), Keeth et al.
patent: 6762974 (2004-07-01), Johnson et al.
patent: 6775755 (2004-08-01), Manning
patent: 6812799 (2004-11-01), Kirsch
Johnson James Brian
Keeth Brent
Lin Feng (Dan)
Mai Son
Micro)n Technology, Inc.
Pencoske Edward L.
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