Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2011-08-23
2011-08-23
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
C712S239000, C712S240000
Reexamination Certificate
active
08006070
ABSTRACT:
An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.
REFERENCES:
patent: 6272666 (2001-08-01), Borkar et al.
patent: 6363490 (2002-03-01), Senyk
patent: 6393374 (2002-05-01), Rankin et al.
patent: 6411156 (2002-06-01), Borkar et al.
patent: 6415388 (2002-07-01), Browning et al.
patent: 6484265 (2002-11-01), Borkar et al.
patent: 6564328 (2003-05-01), Grochowski et al.
patent: 6608528 (2003-08-01), Tam et al.
patent: 6625744 (2003-09-01), Rappoport
patent: 6697932 (2004-02-01), Yoaz
patent: 6762629 (2004-07-01), Tam et al.
patent: 6788156 (2004-09-01), Tam et al.
patent: 6908227 (2005-06-01), Rusu et al.
patent: 6931559 (2005-08-01), Burns et al.
patent: 7035997 (2006-04-01), Musoll
patent: 7627742 (2009-12-01), Bose et al.
patent: 2001/0014928 (2001-08-01), Chrysos et al.
patent: 2002/0099926 (2002-07-01), Sinharoy
patent: 2003/0117759 (2003-06-01), Cooper
patent: 2003/0126478 (2003-07-01), Burns et al.
patent: 2003/0126479 (2003-07-01), Burns et al.
patent: 2003/0188211 (2003-10-01), Chen
patent: 2003/0204762 (2003-10-01), Lee et al.
patent: 2004/0003215 (2004-01-01), Krimer
patent: 2004/0010679 (2004-01-01), Moritz et al.
patent: 2004/0071184 (2004-04-01), Naveh et al.
patent: 2004/0148528 (2004-07-01), Silvester et al.
patent: 2004/0158771 (2004-08-01), Garnett et al.
patent: 2005/0044434 (2005-02-01), Kahle et al.
patent: 2005/0102544 (2005-05-01), Brewer et al.
patent: 2005/0138438 (2005-06-01), Bodas
patent: 2005/0166075 (2005-07-01), Hack
patent: 2005/0235170 (2005-10-01), Atkinson
patent: 2005/0283624 (2005-12-01), Kumar et al.
patent: 2006/0020831 (2006-01-01), Golla et al.
patent: 2006/0101238 (2006-05-01), Bose
patent: 2007/0156995 (2007-07-01), Kaburlasos
patent: 2008/0263325 (2008-10-01), Kudva
patent: PCT/US99/24194 (2000-05-01), None
US 6,330,680, 12/2001, Browning et at. (withdrawn)
Falcon—“A Low Complexity, High Performance Fetch Unit for Simultaneous Multithreading Processors”, Proceedings of the 10th Annual International Symposium on Computer Architecture, pp. 191-202 (1996).
Grunwald—“Confidence Estimation for Speculation Control”, ACM SIGARCH Computer Architecture News, vol. 26, Issue 3, pp. 122-131 (1998).
Jacobsen—“Assigning Confidence to Conditional Branch Predictions”, Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture; pp. 142-152 (1996).
Swanson—“An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors”, ACM Transactions on Computer Systems, vol. 21, No. 3, pp. 314-340 (2003).
Tullsen—“Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor”, Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, pp. 191-202 (1996).
Crepps—“Improving Multi-Core Architecture Power Efficiency Through EPI Throttling and Asymmetric Multiprocessing”, Technology @ Intel Magazine, pp. 1-11 (Feb. 2006).
Felter—“A Performance-Conserving Approach for Reducing Peak Power Consumption in Server Systems”, ICS'05, pp. 293-302 (Jun. 2005).
Hofstee—“Power Efficient Processor Architecture and The Cell Processor”, IEEE HPCA, pp. 258-262 (Nov. 2005).
Li—“Deterministic Clock Gating for Microprocessor Power Reduction”, High Performance Computer Architecture (HPCA) Proceedings, pp. 113-122 (2003).
Gschwind Michael Karl
Philhower Robert Alan
Yeung Raymond Cheung
Chan Eddie
International Business Machines - Corporation
Kahler Mark P
Partridge William B
Talpis Matt
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