Patent
1996-09-30
1998-04-07
Kriess, Kevin A.
395493, G06F 900
Patent
active
057376042
ABSTRACT:
A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
REFERENCES:
patent: 4679166 (1987-07-01), Berger et al.
patent: 4779187 (1988-10-01), Letwin
patent: 4787032 (1988-11-01), Culley
Culley Paul R.
Izquierdo Javier F.
Jansen Kenneth A.
Miller David A.
Taylor Mark
Compaq Computer Corporation
Kriess Kevin A.
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