Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit
Reexamination Certificate
1998-10-21
2001-02-06
Faber, Alan T. (Department: 2753)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Head amplifier circuit
C360S068000, C360S061000, C327S110000, C327S345000
Reexamination Certificate
active
06185057
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to magnetic storage media and more specifically relates to an improved write driver circuit for writing information to a magnetic storage media.
BACKGROUND OF THE INVENTION
Magnetic storage devices such as computer hard drives write binary information to and read binary information from a magnetic storage media (e.g., a magnetic disc comprising Fe
2
O
3
, NiCo, etc.). Binary information is written to the magnetic storage media by changing the magnetization of domains within the media to either a first magnetization (e.g., representing a binary “1”) or a second magnetization (e.g., representing a binary “0”). Written binary information is read from the magnetic storage media by rotating the magnetized media at a constant velocity and by sensing the time-changing flux produced by each magnetized domain.
Within each magnetic storage device, in addition to the magnetic storage media, a write head is provided that comprises an inductive coil for generating a two-directional or “bipolar” flux which changes the magnetization of the domains within the magnetic storage media between the first and second magnetizations. The bipolar flux is generated via a bipolar current driven through the inductive coil by a write driver circuit.
Typically, the speed of the write driver circuit that drives the inductive write head governs the maximum operating speed (e.g., the maximum read/write time) of a magnetic storage device; and the speed of a write driver circuit is the time required to switch the direction of the current flowing through the inductive coil of the write head as described below with reference to
FIGS. 1A and 1B
.
Magnetic storage devices typically employ a write driver circuit known as an H-driver circuit, such as the H-driver circuit
100
(hereinafter “conventional H-driver
100
”) of FIG.
1
A. The conventional H-driver
100
drives a differential current through a write coil (e.g., write coil
102
) coupled between a first differential output terminal OUT
T
(e.g., “Output True”) and a second differential output terminal OUT
C
(e.g., “Output Complement”) of the H-driver
100
to affect magnetization of a magnetic storage media (not shown) adjacent the write coil
102
. Specifically, a differential input voltage applied between a first differential input terminal IN
T
(e.g., “Input True”) and a second differential input terminal IN
C
(e.g., “Input Complement”) of the H-driver
100
controls the direction of differential current flow through the write coil
102
, and thus the magnetization written to the magnetic storage media (not shown).
A typical differential input voltage might be 500 millivolts centered at −2 volts, so that a “high” input voltage level on either input terminal IN
T
or IN
C
is −1.75 volts and a “low” input voltage level on either input terminal IN
T
or IN
C
is −2.25 volts. Other differential input voltages and center voltages may be employed.
The H-driver
100
further comprises a first pull-down transistor (Q
1
)
104
for pulling the output terminal OUT
C
to a low voltage level with respect to the output terminal OUT
T
(e.g., by sourcing current through the write coil
102
in a first direction as described below) and a second pull-down transistor (Q
2
)
106
for pulling the output terminal OUT
T
to a low voltage level with respect to the output terminal OUT
C
(e.g., by sourcing current through the write coil
102
in a second direction as describe below). The first pull-down transistor
104
has a base lead connected to the input terminal IN
T
, a collector lead connected to the output terminal OUT
C
and an emitter lead connected to a negative voltage rail (V
ee
)
108
via a first current source (J
1
)
110
. The second pull-down transistor
106
has a base lead connected to the input terminal IN
C
, a collector lead connected to the output terminal OUT
T
and an emitter lead connected to the emitter lead of the first pull-down transistor
104
and to the first current source
110
.
Also provided within the H-driver
100
are a first pull-up transistor (Q
5
)
112
for pulling the output terminal OUT
C
to a high voltage level with respect to the output terminal OUT
T
and a second pull-up transistor (Q
6
)
114
for pulling the output terminal OUT
T
to a high voltage level with respect to the output terminal OUT
C
. The first pull-up transistor
112
has a base lead connected to a positive voltage rail (V
CC
)
116
via a first pull-up resistor (R
1
)
118
, a collector lead connected to the positive voltage rail
116
and an emitter lead connected to the output terminal OUT
C
via a first Schottky diode (D
1
)
120
. The high D.C. voltage level for the output terminal OUT
C
, therefore, is approximately V
CC
minus the forward voltage of the first pull-up transistor
112
's base-emitter junction and the forward voltage of the first Schottky diode
120
(neglecting the IR drop associated with the first pull-up resistor
118
). The second pull-up transistor
114
has a base lead connected to the positive voltage rail
116
via a second pull-up resistor (R
2
)
122
, a collector lead connected to the positive voltage rail
116
and an emitter lead connected to the output terminal OUT
T
via a second Schottky diode (D
2
)
124
. The high D.C. voltage level for the output terminal OUT
T
, therefore, is approximately V
CC
minus the forward voltage of the second pull-up transistor
114
's base-emitter junction and the forward voltage of the second Schottky diode
124
(neglecting the IR drop from the second pull-up resistor
122
). The first and the second Schottky diodes
120
and
124
protect the base-emitter junctions of the first and the second pull-up transistors
112
and
114
, respectively, from being reverse biased and damaged during switching of the current flow direction through the write coil
102
(as described below).
The H-driver
100
further comprises a third pull-down transistor (Q
3
)
126
and a fourth pull-down transistor (Q
4
)
128
for pulling to a low voltage level the base lead of the first pull-up transistor
112
and the base lead of the second pull-up transistor
114
, respectively. The third pull-down transistor
126
has a base lead connected to the input terminal IN
T
, a collector lead connected to the base lead of the first pull-up transistor
112
and an emitter lead connected to the negative voltage rail
108
via a second current source (J
2
)
130
. A third Schottky diode (D
3
)
132
is connected between the collector of the third pull-down transistor
126
(forming a first node
134
) and ground for preventing the first node
134
from being pulled below ground by more than the forward voltage (e.g., about 0.4-0.5 volts) of the third Schottky diode
132
.
The fourth pull-down transistor
128
has a base lead connected to the input terminal IN
C
, a collector lead connected to the base lead of the second pull-up transistor
114
and an emitter lead connected to the emitter lead of the third pull-down transistor
126
and to the second current source
130
. A fourth Schottky diode (D
4
)
136
is connected between the collector of the fourth pull-down transistor
128
(forming a second node
138
) and ground for preventing the second node
138
from being pulled below ground by more than the forward voltage (e.g., about 0.4-0.5 volts) of the fourth Schottky diode
136
.
In operation, if a high voltage level is applied to the input terminal IN
T
and a low voltage level is applied to the input terminal IN
C
, the high voltage level applied to the input terminal IN
T
turns ON the first and the third pull-down transistors
104
and
126
by forward biasing each transistor's base-emitter junction. Currents J
1
and J
2
(from the first and second current sources
110
and
130
, respectively) thereby are caused to flow through the first and the third pull-down transistors
104
and
126
, respectively.
In steady-state, with the third pull-down transistor
126
ON, the first node
134
is pulled to a low voltage l
Faber Alan T.
International Business Machines - Corporation
Schmeiser Olsen & Watts
Shkurko Eugene I.
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