Method and apparatus for increasing the speed of memory access i

Details Method and apparatus for increasing the speed of memory access i Method and apparatus for increasing the speed of memory access i

1993-04-12

1993-11-23

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642434, 3642543, G06F 1210

Patent

active

052652360

ABSTRACT:
In the memory access unit of the present invention, the memory request logic is centralized in the memory management unit (MMU). The MMU instructs the MCU, which interfaces directly with the DRAMs, on the type of memory access to perform. By centralizing the memory requests, the MMU is able to maintain an account of each memory access, thereby providing the MMU the means to determine if a memory access fulfills the requirements of a fast page mode access before a request is made to the MCU. The MMU comprises the row address comparator which can execute the row address comparison in parallel with the cache lookup. Therefore, if the cache lookup determines a memory access is required, a specific fast page mode memory access request can be made, without the memory controller incurring the additional delay of checking the row address. Thus, by using the memory access unit of the present invention, the system can default to fast page mode access without the additional penalty normally incurred by comparing the row address in a serial manner.

REFERENCES:
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patent: 4847758 (1989-07-01), Olson et al.
patent: 4872138 (1989-10-01), Ciacci
patent: 4924375 (1990-05-01), Fung et al.
patent: 4933910 (1990-06-01), Olson et al.
patent: 5034917 (1991-07-01), Bland et al.
patent: 5051889 (1991-09-01), Fung et al.

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