Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
2006-02-01
2010-11-02
Shah, Kamini S (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C703S013000, C703S026000, C703S028000, C710S312000, C717S135000, C717S138000, C716S030000, C716S030000
Reexamination Certificate
active
07827023
ABSTRACT:
A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.
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Beausoleil William F.
Elmufdi Beshara G.
Poplack Mitchell G.
Su Tai
Cadence Design Systems Inc.
Moser IP Law Group
Patel S.
Shah Kamini S
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