Method and apparatus for increasing the decoding speed of a micr

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3642288, 3642287, 3642295, 3642306, 3642318, 36423221, 3642606, 3642607, 3642609, 3642624, 3642633, 36426281, 364DIG1, 364DIG2, 395375, G06F 924, G06F 930, G06F 934, G06F 938

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053966341

ABSTRACT:
Apparatus for increasing the decoding speed of a microprocessor. The apparatus includes a first decoder for decoding macroinstructions. The first decoder includes apparatus for generating a single initial microinstruction vector from simple macroinstructions and from complex macroinstructions having a beginning microinstruction equivalent to a microinstruction for a simple macroinstruction. The first decoder also includes apparatus for indicating a beginning address for generating any remaining microinstruction vectors for a complex macroinstruction decoded by the first decoder. The apparatus for increasing the decoding speed of a microprocessor also includes apparatus, coupled to the first decoder, for generating any remaining microinstruction vectors for complex macroinstructions decoded by the first decoder. The apparatus for generating any remaining microinstruction vectors includes apparatus for responding to the apparatus for indicating a beginning address.

REFERENCES:
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5155817 (1992-10-01), Kishigami et al.
patent: 5222244 (1993-06-01), Carbine et al.

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