Method and apparatus for increasing system throughput via an inp

Details Method and apparatus for increasing system throughput via an inp Method and apparatus for increasing system throughput via an inp

1988-06-27

1991-03-26

Eng, David Y.

Boots, shoes, and leggings

3642423, 3642383, 3642426, G06F 1300

Patent

active

050034650

ABSTRACT:
In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

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