Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
1999-09-01
2001-07-03
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
C327S566000, C361S767000, C361S783000, C257S723000
Reexamination Certificate
active
06255899
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits chips, and more specifically to a method and apparatus for increasing the frequency at which semiconductor integrated circuit chips may communicate (i.e., interchip communications rate).
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit chips (hereinafter “IC chips”) typically are mounted to and communicate via a chip carrier formed from a ceramic (e.g., alumina), an epoxy-glass (e.g., an organic epoxy) or a glass-ceramic. To allow interchip communications, metallic signal lines are provided within the chip carrier that interconnect the pads or pins of the chips mounted thereon.
Due to loading from a combination of chip/chip package resistance, inductance and capacitance, carrier mounted chips operating at high clock rates (e.g., about 500 MHZ to 1 GHZ) typically communicate with other carrier mounted chips at a maximum rate of about 50% of each chip's clock rate (e.g., about 250 MHZ to 500 MHZ). Often significantly lower communications rates must be employed at a significant bandwidth loss. Interchip wiring length differences also limit maximum interchip communications rates for carrier mounted chips (e.g., due to distortion/skew concerns). Accordingly, a need exists for a method and apparatus for increasing interchip communications rates.
SUMMARY OF THE INVENTION
To address the needs of the prior art, an inventive assembly is provided that comprises an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line (e.g., for delivering speed critical signals such as timing signals, data signals, address signals, etc.) extending directly through the interposer from the first surface to the second surface. The interposer may comprise a ceramic, an epoxy glass, a glass ceramic, silicon, silicon-on-insulator or any other suitable material.
A first IC is coupled to the first surface of the interposer and has a first external connection mechanism (e.g., a pin or a pad of the first IC) coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals (e.g., power, ground, those between peripheral devices and the microprocessor, etc.) thereto or for receiving such signals therefrom.
A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC (e.g., for delivering signals therebetween). The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line (e.g., a speed critical signal line, a carrier signal line, a non-speed critical signal line, etc.).
Because of the short signal line length of the at least one speed critical signal line (e.g., the thickness of the interposer, preferably about 5 mm) and the low inductive, capacitive and resistive loading associated therewith, speed critical signals may be transferred across the at least one speed critical signal line at the maximum clock rate of the first IC and the second IC, and small, faster drivers may be employed. Skew rate also is reduced due to the short signal line length.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.
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Bertin Claude L.
Bonaccio Anthony R.
Hedberg Erik L.
Kalter Howard L.
Maffitt Thomas M.
Cunningham Terry D.
Dugan & Dugan
International Business Machines - Corporation
Nguyen Long
Peterson Peter W.
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