Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2002-08-29
2003-11-11
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S003000
Reexamination Certificate
active
06646478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits, and, more specifically, to phase detection circuits.
2. Description of Related Art
A PLL (phase locked loop ) refers to a feedback loop in which the input and the feedback parameters of interest are the relative phases of the waveforms. The function of a PLL is to track small differences in phase between the input and feedback signal. A conventional PLL typically includes a phase detector, low-pass filter and a VCO (voltage-controlled oscillator). The phase detector measures the phase difference between its two inputs. The phase detector output is then filtered by the low-pass filter and applied to the VCO. The VCO input voltage changes the VCO frequency in a direction that reduces the phase difference between the input signal and the local oscillator. The loop is in phase lock or locked when the phase difference between the input signal and the VCO frequency is reduced to zero.
A phase detector only accepts phase information in comparing two signals. A PFD (phase/frequency detector) is also able to accept frequency information in comparing two signals. A digital PLL is a PLL system in which the VCO and loop filter are built from digital components such as gates or flip-flops. A PFD is typically made from an exclusive OR gate, or an AND gate and D-type flip-flops or a tri-state phase/frequency comparator. PLL circuits have two ranges for acquisition, a pull-in range and a capture range (also known as lock-in range). The acquisition time is the total time the PLL takes to acquire both frequency and phase lock.
A PLL circuit will produce the lowest output jitter level if it can perform phase comparisons and can phase lock using the highest input clock available. As phase measurements become more regular, the loop is updated more regularly and control is thereby maintained to reduce internal noise. Unfortunately, some systems, such as telecommunications networks, require the PLL system to be tolerant to a large amount of jitter on the clock input and still be able to maintain a lock. To maintain a lock, the system must remember the location of the 0° position and continuously pull the PLL in the direction of that location. Often the required jitter tolerance values will extend to tens of clock cycles or unit intervals (1 unit interval (UI)=1 clock cycle=360°). A conventional PLL would not be able to maintain a lock with over ±1 UI of jitter on the input. Thus, with ±10 UI of input jitter, the PLL would not know the location of the original 0° position and, as a result, cycle slippage would occur. Cycle slippage causes timing problems for the system, such as, for example, buffer overflows. Accordingly, conventional PLL circuits may not meet the requirements of systems that require a high jitter tolerance, such as telecommunications systems. Jitter tolerance is particularly difficult to provide in high frequency applications. Conventional techniques for providing jitter tolerance for high frequency applications include dividing the clock down to a fraction of the original frequency. Although the lower frequency results in proportionately lower jitter, the system suffers a loss in performance.
FIG. 10
shows a conventional type-4 PFD, indicated generally at
500
, with a pair of output sampling DFF (D-type flip flop) units
505
and
510
(“Down_s” and “Up_s”, respectively). The output sampling DFF units
505
and
510
are optional and would not be needed in an APLL (analog PLL) system. Note that AND gate
525
(“I1”) and inverter
530
(“I2”), shown in
FIG. 10
, are idealized representations and in reality would incorporate some delay so that the reset pulse lasts for a sufficient duration, typically a few nanoseconds, to effectively reset DFF units
535
and
540
. Generally, the output of DFF units
535
and
540
each go high on the leading edge of their respective clock inputs and remain high until they are reset. The reset signal occurs when inputs A
515
and B
520
have both gone from a low to a high state, which makes signals ‘up’ and ‘down’ both high. When both input signals A
515
and B
520
are in phase and of the same frequency, both outputs will be low for most of the time, with signals ‘up’ and ‘down’ both pulsing high only for a few nanoseconds, and no signal will be applied to the VCO (not shown in FIG.
10
). If the two signal frequencies are not the same, then the output pulse widths will depend on both the relative frequency difference and the phase difference. The type-4 PFD
500
is common because of its simplicity, accuracy and ability to perform both frequency and phase locking. But, the phase capture range of the type-4 PFD is generally limited to ±360°.
FIGS. 11 and 12
show timing diagrams that illustrate the behavior of conventional PFD
500
shown in FIG.
10
. If the rising edge of input A
515
, shown in
FIG. 11
, occurs before the rising edge of input B
520
, then the “up” pulse is wider than the “down” pulse, as shown in FIG.
11
. The width of the up pulse is proportional to the phase difference between input A
515
and input B
520
. Conversely, if the rising edge of input B
520
occurs before the rising edge of input A
515
, then the down pulse is wider and has a width proportional to the phase difference. An inspection of
FIG. 10
in conjunction with the timing diagrams shown in
FIGS. 11-12
reveals that the inherent range of the conventional PFD
500
is limited to one cycle or UI as discussed above. The diagram shown in
FIG. 12
shows the waveforms at the extreme ±360° limit. Beyond this limit, the signal begins to resemble that of FIG.
11
. At this point, the 0° reference point has been lost and a cycle slip has occurred. Thus, PFD
500
is unable to operate past ±360°. Therefore it would be desirable to provide a phase detection circuit that provides an operating range that extends beyond ±360° and provides a large amount of jitter tolerance.
SUMMARY OF THE INVENTION
The present invention provides a phase detection circuit that allows the capture range, lock range and jitter tolerance to be extended beyond the ±360° limit associated with conventional PLL circuits. In an embodiment of the invention, the phase detection circuit includes a PFD (phase and frequency detector) that operates in the ±540° range.
In another exemplary embodiment of the invention, the phase detection system combines two types of phase detectors, including a coarse phase detector and a fine phase detector, e.g., the PFD, in an advantageous manner. The phase detection system uses the coarse phase detector, e.g., a digital cycle slip counter phase detector, to provide a wide phase capture and lock range for a large jitter tolerance. The phase detection system combines this detector with a fine phase measurement from the PFD for very accurate phase control and low output jitter.
The PFD allows the coarse phase detector to precondition the PFD so that the coarse and fine detectors work together with no conflict in responses and no dead-band, e.g., phase ranges not captured by either detector. The capture range for the presently disclosed phase detection circuit may be extended in programmable amounts up to several thousand clock cycles or can be set to any desired maximum capture range in steps of 360°. In an exemplary embodiment of the invention, the system and method of the present invention may be implemented in PLL systems that have some digital component such that the logical merging and arithmetic combining of phase detector results may be more easily accomplished with the digital components than with analog components.
The presently disclosed phase detection system provides a number of advantages over conventional phase detection circuits. One advantage of the present phase detection system is a wide phase capture and lock range with an unlimited maximum phase capture range. Another advantage is that the system provides accurate phase measurement in addition to the wide range. A
O'Melveny & Myers LLP
Semtech Corporation
Wells Kenneth B.
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