Patent
1992-06-05
1995-04-18
Beausoliel, Jr., Robert W.
395425, G06F 1110
Patent
active
054086442
ABSTRACT:
A posting memory used in conjunction with a drive array to increase the performance of fault tolerant disk array write operations. When the posting memory flushes dirty data back to the disk array, the posting memory coalesces or gathers contiguous small write or partial stripe write requests into larger, preferably full stripe writes. This reduces the number of extra read operations necessary to update parity information. In this manner, the actual number of reads and writes to the disk array to perform the transfer of write data to the disk array is greatly reduced. In addition, when the posting memory is full, the posting memory delays small, i.e., partial stripe writes but allows full stripe writes or greater to pass directly to the disk array. This reduces the frequency of partial stripe writes and increases disk array performance.
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Flower David L.
Schneider Randy D.
Beausoliel, Jr. Robert W.
Compaq Computer Corporation
Wright Norman M.
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