Method and apparatus for improving SRAM write operations

Details Method and apparatus for improving SRAM write operations Method and apparatus for improving SRAM write operations

2011-06-28

2011-06-28

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Associative memories

Flip-flop

C365S154000, C365S189050

Reexamination Certificate

active

07969759

ABSTRACT:
A memory cell includes a first access transistor, first and second pull-up transistors, a depletion transistor, and first and second pull-down transistors. The first access transistor is connected to a word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and to the first data node and the second pull-down transistor is connected to the depletion transistor and to the second data node. The depletion transistor is connected to the word line and to the second power supply point.

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