Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2002-11-07
2004-12-28
Dang, Phuc T. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S713000, C257S777000
Reexamination Certificate
active
06835991
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to photolithographic processing, and in particular to methods of controlling the formation of objects on a semiconductor wafer.
BACKGROUND OF THE INVENTION
Most modern integrated circuits are created by photolithographic techniques whereby selected portions of a silicon wafer are exposed to illumination light. The particular areas that are exposed on the wafer are generally determined by a mask or reticle having opaque and clear areas that block or pass the illumination light.
As the size of the features to be created on the wafer become smaller and smaller, the features can become distorted due to optical effects, such as diffraction or destructive interference of the light passing through the mask or reticle. Another distortion can occur as a result of setting the exposure time/intensity for the wafer.
FIG. 1
illustrates a portion of a semiconductor mask or reticle having a number of elements
10
that are relatively widely spaced or isolated from one another. For example, these elements may represent interconnect wires to be created within an integrated circuit. Additionally, the mask or reticle includes a number of elements
12
that are closely grouped with one another. If the exposure of the mask or reticle is set such that the isolated elements
10
are properly imaged on the wafer, then it often happens that the relatively closely grouped elements
12
will be incorrectly exposed. Conversely, if the exposure of the mask or reticle is set such that the closely grouped elements
12
are properly formed on the wafer, then the isolated elements
10
will be incorrectly exposed. In many instances, it is virtually impossible to select an exposure of the mask or reticle that will optimize the formation of closely grouped and isolated circuit elements on a wafer.
SUMMARY OF THE INVENTION
To address the problems discussed above, the present invention is a method for controlling the creation of closely spaced objects on a wafer during photolithographic processing. A mask or reticle has a substantially uniform pattern of features disposed thereon and the exposure of the mask or reticle is chosen such that objects created by the uniform feature pattern is optimized. The uniform pattern of features on the mask/reticle creates a corresponding uniform pattern of objects on a wafer. Selected objects can then be used as desired to provide the desired functionality.
In one embodiment of the invention, the substantially uniform feature pattern comprises a number of uniformly spaced lines that form interconnect wires on an integrated circuit. Interconnect wires of specific lengths are created by terminating the lines at desired points on the mask or reticle. Alternatively, wire of specific length can be created by exposing the wafer at the desired endpoints of the wires.
In another embodiment of the invention, the circuit elements to be created are gate electrodes. A mask or reticle has substantially uniform pattern of strips that create gate electrodes over semiconductor wells. Individual gate electrodes are made by terminating the lines at desired locations either on the mask or reticle itself, or on the wafer.
REFERENCES:
patent: 4348105 (1982-09-01), Caprari
patent: 5508803 (1996-04-01), Hibbs et al.
patent: 5864162 (1999-01-01), Reedy et al.
patent: 5872380 (1999-02-01), Rostoker et al.
patent: 6136652 (2000-10-01), Hazani
patent: 6143655 (2000-11-01), Forbes et al.
patent: 6150256 (2000-11-01), Furukawa et al.
patent: 6189131 (2001-02-01), Graef et al.
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6221751 (2001-04-01), Chen et al.
patent: 6245083 (2001-06-01), Liu
patent: 6262426 (2001-07-01), Zafiratos
patent: 6294460 (2001-09-01), Subramanian et al.
patent: 6338922 (2002-01-01), Liebmann et al.
patent: 6344379 (2002-02-01), Venkatraman et al.
patent: 6365509 (2002-04-01), Subramanian et al.
Asai, S. et al., “High performance optical lithography using a separated light source,” J. Vac. Sci. Technol. B 10(6), Nov./Dec. 1992.
Garofalo, J. et al., “Mask assisted off-axis illumination technique for random logic,” J. Vac. Sci. Technol. B 11(6), Nov./Dec. 1993.
Liu, Y. et al., “Binary and Phase-shifting Image Design for Optical Lithography,” SPIE vol. 1463 Optical/Laser Microlithography IV (1991).
Liu, Y. et al., “Binary and Phase Shifting Mask Design for Optical Lithography,” IEEE Transactions on Semiconductor Manufacturing, 5(2), May 1992.
Nashold, K. et al., “Image construction through diffraction-limited high-contrast imaging systems: an iterative aproach,” J. Opt. Soc. Am. A, 2(5), May 1985.
Saleh, B. et al., “Image construction: optimum amplitude and phase masks in photolithography,” Applied Optics, 24(10), May 15, 1985.
Saleh, B. et al., “Pre-inverse filtering of distorted images,” Applied Optics, 20(22), Nov. 15, 1981.
Saleh, B. et al., “Reduction of errors of microphotographic reproductions by optimal corrections of original masks,” Optical Engineering, 20(5), Sep./Oct. 1981.
Prouty, M., “Optical Imaging with Phase Shift Masks,” SPIE vol. 470, Optical Microlithography III: Technology for the Next Decade, 1984.
Tamechika, E., “Resolution Improvement Using Auxiliary Pattern Groups in Oblique Illumination Lithography,” Jpn. J. Appl. Phys., vol. 32 (1993) pp. 5856-5862, Part I, No. 12B, Dec. 1993.
Terasawa, T. et al., “0.3-micron optical lithography using a phase-shifting mask,” SPIE vol. 1088, Optical/Laser Microlithography II, 1989.
Terasawa, T. et al., “Improved resolution of an I-line stepper using a phase-shifting mask,” J. Vac. Sci. Technol. B 8(6), Nov./Dec. 1990.
Wyant, J., “Image Processing I,” J. Opt. Soc. Am. 70(12), 1580, 1980.
LandOfFree
Method and apparatus for improving resolution of objects in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for improving resolution of objects in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving resolution of objects in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3308202