Photography – Fluid-treating apparatus – Heating – cooling – or temperature detecting
Reexamination Certificate
2002-02-06
2003-06-10
Mathews, Alan A. (Department: 2851)
Photography
Fluid-treating apparatus
Heating, cooling, or temperature detecting
C396S611000, C396S625000, C396S626000, C396S633000, C134S902000
Reexamination Certificate
active
06575645
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention is related to the developing of a selectively exposed layer of resist formed on an integrated circuit wafer and more particularly to stopping the developing process and removing the resist using immersion in de-ionized water followed by a vacuum dry period. The vacuum dry period may also include heating the wafer using a heat lamp.
(2) Description of the Related Art
U.S. Pat. No. 4,902,608 to Lamb et al. and U.S. Pat. No. 5,025,280 to Lamb et al. describes a method and apparatus for immersing a selectively exposed layer of photoresist on a wafer first in a bath of developer and next in a bath of de-ionized water. While the wafer is in the de-ionized water it is slowly turned in the water. The wafer is then removed from the water and rapidly spun to spin dry the wafer and photoresist.
U.S. Pat. No. 4,982,215 to Matsuoka describes a developing process where a workpiece having a resist layer is immersed in a bath of developer at a first temperature. Electrical current between the workpiece and an electrode also immersed in the developer to monitor the progress of the developing process. When the developing process has been completed an additional amount of developer at a second temperature, lower than the first temperature, is added to the original developer as the withdrawl of the developer is begun. The progress of the development is thus retarded providing precision for the endpoint of the development process.
This invention describes a method and apparatus for developing a resist pattern that does not require spinning the wafer and does not require batches of developer at different temperatures.
SUMMARY OF THE INVENTION
Resist patterns are routinely used in the manufacture of integrated circuit wafers. These resist patterns are formed by selectively exposing a layer of resist, using photolithography or electron beam methods or the like, and developing the selectively exposed layer of resist to form the pattern. Developing the resist is carried out by placing the exposed resist in contact with liquid developer material for a certain time followed by washing the developer away with de-ionized water, or other cleaning liquid. The de-ionized water is then removed by drying the resist pattern.
As the level of integration of integrated circuits increases problems are encountered with the conventional method of developing resist patterns. Some of the problems encountered developing resist patterns will be described with reference to
FIGS. 1-3
.
FIG. 1
shows the top view of an integrated circuit wafer with a layer of selectively exposed resist formed thereon and liquid developer material placed on the layer of selectively exposed resist
10
.
FIG. 2
shows a cross section view of the integrated circuit wafer of along the line
2
-
2
′ of FIG.
1
.
FIG. 2
shows the integrated circuit wafer
12
placed on a wafer holder
18
. The layer of selectively exposed resist
14
is formed on the integrated circuit wafer
12
. Liquid developer material
16
is placed on the layer of resist
14
. The wafer holder
18
is attached to a shaft
20
.
FIG. 3
shows a cross section view of the integrated circuit wafer after the developing of the exposed resist has been completed. The layer of resist has been developed forming a resist pattern
15
. The shaft
20
attached to the wafer holder
18
is attached to a means
22
for spinning the shaft
20
, wafer holder
18
, integrated circuit wafer
12
, and developed resist pattern
15
as indicated by the rotational arrow
36
. As the spinning of the wafer begins, and is still at a low speed, valves
27
and
29
are opened and de-ionized water is fed from a de-ionized water supply
26
through a pipe
28
to nozzles
30
which spray de-ionized water on the developed resist pattern
15
forming a layer of deionized water
24
over the resist pattern. De-ionized water is also directed from the de-ionized water supply
26
through a pipe
32
to a nozzle
34
to spray de-ionized water on the back side of the wafer. The valves
27
and
29
are then closed stopping the supply of de-ionized water to the integrated circuit wafer. The wafer is then spun at high speed to dry the wafer, thereby removing any residual de-ionized water. In this conventional developing method the de-ionized water, or other cleaning liquid, imparts a force to the fine elements of the resist pattern as the wafer is spun at high speeds often damaging the resist pattern.
It is a principle objective of this invention to provide a method of developing and cleaning a layer of selectively exposed resist which will avoid damage to the developed resist pattern.
It is another principle objective of this invention to provide an apparatus for developing and cleaning a layer of selectively exposed resist which will avoid damage to the developed resist pattern.
These objectives are achieved by immersing the integrated circuit wafer with developer on the resist pattern in de-ionized water after developing the resist pattern has been completed. There is no spinning of the wafer however low levels of ultrasonic power may be used. The wafer is then removed from the de-ionized water and the chamber containing the wafer is evacuated, using a means such as a vacuum pump, to dry the wafer. Heat, using a means such as a heating lamp, may be applied to the wafer while the chamber is evacuated. During the developing process no force is exerted on the resist pattern by the cleaning liquid, damage to the pattern is avoided, and a wider choice of resists is available.
REFERENCES:
patent: 4429983 (1984-02-01), Cortellino et al.
patent: 4633804 (1987-01-01), Arii
patent: 4902608 (1990-02-01), Lamb et al.
patent: 4982215 (1991-01-01), Matsuoka
patent: 5025280 (1991-06-01), Lamb et al.
patent: 5175124 (1992-12-01), Winebarger
patent: 5227001 (1993-07-01), Tamaki et al.
patent: 5368054 (1994-11-01), Koretsky et al.
patent: 5650251 (1997-07-01), Ishiwata et al.
patent: 5718763 (1998-02-01), Tateyama et al.
patent: 5762708 (1998-06-01), Motoda et al.
patent: 5853961 (1998-12-01), Sakai et al.
patent: 9-69488 (1997-03-01), None
Ackerman Stephen B.
Mathews Alan A.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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