Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2000-04-03
2003-05-13
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S120000, C702S123000, C702S118000, C714S025000, C714S028000, C703S015000, C703S023000, C703S027000, C375S130000, C375S140000
Reexamination Certificate
active
06564162
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the electrical verification of devices, such as microprocessors, digital signal processing (DSP) devices, and application specific integrated circuits (ASICs), that are capable of emulating their own results, and more particularly to a method and apparatus for improving electrical verification throughput of such devices by comparison of operating-point differentiated test results.
BACKGROUND OF THE INVENTION
Electrical verification of devices is performed to detect various electrical failures or weaknesses, as opposed to functional failures, of the devices. Electrical failures or weaknesses may be considered to be related to the electrical parameters, such as frequency, voltage, or temperature, that define the operating point under which a device must operate. The electrical robustness and reliability of the device may therefore be tested by subjecting the device to particular code sequences that are designed to test the electrical parameters of the device. Functional verification, as opposed to electrical verification, is concerned with uncovering functional failures that are indicative of design flaws of a device.
To date, electrical verification of devices that are capable of emulating their own results, such as microprocessors, digital signal processing (DSP) devices, and application specific integrated circuits (ASICs), has been heavily dependent upon software emulation of the device to generate predicted results against which actual results, generated by actually running an appropriate test case or code sequence on the device itself, can be compared. The comparison of actual and predicted test results provides an indication of how well the device is performing. A major drawback of this approach to electrical device verification is that it is inherently slow due to the vast majority of time that is spent in software emulation generating the predicted results. A related concern is the problem of tracking down emulation problems, commonly known as “emulation bugs,” that are often associated with software emulation.
There is therefore an unmet need in the art to be able to enhance electrical verification of devices by lessening the dependence upon software emulation and testing using known good devices. Such an approach can be expected to lessen the time required for electrical verification, minimize the occurrence of emulation bugs, and otherwise render a more efficient electrical verification process.
SUMMARY OF THE INVENTION
Therefore, according to the present invention, a method, embodied within a computer program of a computer-readable medium or otherwise, for improving electrical verification of a device employs operating-point differentiated testing. The method minimally comprises generating a code sequence, generating predicted results running the code sequence, switching the device from a first to a second operating point by changing a parameter of the first operating point to define the second operating point, running the code sequence at the second operating point to generate actual results, and comparing the actual results to the predicted results to determine if they match. Some indication of the results, such as an error message that is displayed or printed, may follow. If the actual results do not match the predicted results, software emulation of the code sequence may be performed to verify the predicted results. Predicted results may be generated by software emulation of the code sequence or by running the code sequence on the device at the first operating point.
The methodology of the present invention is made more robust by permuting the code sequence, either by permuting an initial context in which the code sequence operates or by permuting the code sequence itself, and by generating multiple code sequences. The methodology can thus additionally include comparing a permute index to the number and, if the permute index is less than the number of permutes to be performed, permuting the code sequence to generate a permuted code sequence. The methodology is then performed on the permuted code sequence and the permute index is incremented. Additional code sequences are generated by comparing a sequence index to a number of sequences to be generated and, if the sequence index is less than the number of sequences, generating a new code sequence on which the methodology is performed.
REFERENCES:
patent: 5991529 (1999-11-01), Cox et al.
patent: 6349399 (2002-02-01), Mannning
Desta Elias
Hewlett--Packard Company
Hoff Marc S.
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