Boots – shoes – and leggings
Patent
1995-12-27
1998-10-13
Voeltz, Emanuel Todd
Boots, shoes, and leggings
364489, 364490, G06F 1750
Patent
active
058222170
ABSTRACT:
A method and apparatus for improving the retiming of a circuit. The invention "tricks" a conventional retiming engine so that the retiming engine will correctly and consistently retime the circuit. Specifically, the present invention adjusts gate delays to account for the fact that registers in the circuit may be moved during retiming. The present invention also includes a methodology for choosing a preferred register from a technology library. Lastly, the present invention also adjusts the clock period of the circuit to account for the fact that the retiming engine assumes a clock-to-state of registers in the circuit to be zero when this is not always the case.
REFERENCES:
patent: 5448497 (1995-09-01), Ashar et al.
patent: 5544066 (1996-08-01), Rostoker et al.
patent: 5553000 (1996-09-01), Dey et al.
patent: 5555188 (1996-09-01), Chakradhar
Martin ("Retiming by combination of relocation and clock delay adjustment", IEEE Comput. Soc. Press, Proceedings EURO-DAC, European Design Automation Conference with EURO-VHDL 1993, pp. 384-389), Sep. 20, 1993.
Soyata et al. ("Monotonicity constraints on path delays for efficient retiming with localized clock skew and variable register delay", IEEE Symposium on Circuits and Systems, 28 Apr.-3 May 1995 Conference, pp. 1748-1751), Apr. 28, 1995.
Soyata et al. ("Integration of clock skew and register delays into a retiming algorithm", IEEE, Proceedings of 1993 IEEE International Symposium on Circuits and Systems, May 3-6, 1993, pp. 1483-1486), May 3, 1993.
De Micheli, ("Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization", IEEE Transactions on Computer-Aided Design, vol. 10, No. 1, pp. 63-73), Jan. 1991.
Soyata et al. ("Synchronous performance and reliability improvement in pipelined ASICs", IEEE Proceedings: Seventh Annual IEEE International ASIC Conference and Exhibit, 19-23 Sep. 1994, pp. 383-390).
Article by Shenoy et al., entitled "Efficient Implementation of Retiming" pp. 1-20, publication date unknown.
Kik Phallaka
Synopsys Inc.
Todd Voeltz Emanuel
LandOfFree
Method and apparatus for improving circuit retiming does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for improving circuit retiming, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving circuit retiming will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-319945