Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-10-19
2001-07-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030
Reexamination Certificate
active
06262913
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates generally to electronic counters. More particularly, the present invention relates to electronic counters that are implemented using memory devices or cells that wear out after extended use. Even more particularly, the present invention relates to a novel electronic counter that prolongs the useful life of memory cells used for implementing the counter.
II. Description of the Related Art
Non-volatile memory devices, such as EEPROMs, have memory cells that wear out. When cells in such non-volatile memory devices are used for implementing a typical counter that is written to continuously, the memory cells representing the least significant bits of the counter will be written to most often and will often wear out quickly as result of such use. As the memory cells wear out, new storage locations must be allocated to hold the counter. Since in many electronic devices the amount of available non-volatile memory cells is limited, allocation of additional memory cells to a counter in order to compensate for worn-out cells is undesirable. In view of this, it would be advantageous to provide a counter that could be implemented in non-volatile memory and that minimized the wear on the memory cells used for the counter.
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus for updating and storing a counter value. In response to each of a plurality of N counter update signals, a binary memory cell is selected from a plurality of binary memory cells and the state of the selected binary memory cell is inverted. After the N counter update signals are received, a register that is separate from the plurality of binary memory cells is incremented, and the process is then repeated in response to further counter update signals. Each of the plurality of binary memory cells is inverted on average an equal number of times during each repetition of the process. The states of the plurality of binary memory cells and the value in the register represent the counter value at any given time.
In accordance with a preferred embodiment, a conversion table is used to facilitate the determination of the counter value at any given time. In this embodiment, an index value is determined by applying the states of the plurality of binary memory cells to a conversion table. The counter value is then determined by summing the index value and a cycle count value. The counter value can also be determined by summing the index value, the cycle count value and an offset value.
In accordance with a further aspect, the present invention can be used to extend the life of a counter in cases when one or more individual memory cells in the counter become inoperative. In this embodiment, after one of the plurality of binary memory cells is identified as being inoperative, the conversion table is modified in response to the inoperative binary memory cell, and the inoperative binary memory cell is removed from the plurality of binary memory cells that may selected during subsequent repetitions of the process.
REFERENCES:
patent: 4512029 (1985-04-01), Brice
patent: 4584647 (1986-04-01), Eckert
patent: 5088061 (1992-02-01), Golnabi, et al.
patent: 5974485 (1999-10-01), Kruschinski
patent: 6038165 (2000-03-01), Miwa et al.
patent: 0854425 (1997-11-01), None
Hutchison, IV James A.
Spall Lee
Brown Charles D.
Nelms David
Qualcomm Incorporated
Streeter Tom
Tran M.
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