Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1997-09-03
1999-09-14
Utech, Benjamin
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438692, 438694, H01L 21302
Patent
active
059522410
ABSTRACT:
A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.
REFERENCES:
patent: 5401691 (1995-03-01), Caldwell
patent: 5503962 (1996-04-01), Caldwell
patent: 5614446 (1997-03-01), Ramaswami et al.
patent: 5627110 (1997-05-01), Lee et al.
patent: 5783490 (1998-07-01), Tseng
Baker Daniel Claire
Drill Charles Franklin
Weling Milind Ganesh
Chen Kin-Chan
Utech Benjamin
VLSI Technology Inc.
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