Patent
1998-07-15
2000-08-08
Lintz, Paul R.
39550035, G06F 1750
Patent
active
061013234
ABSTRACT:
A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.
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Liebmann S. Peter
Quarles Thomas L.
Spruiell Leslie D.
Antrim Design Systems, Inc.
Garbowski Leigh Marie
Lintz Paul R.
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