Method and apparatus for improved metal-insulator-semiconductor

Details Method and apparatus for improved metal-insulator-semiconductor Method and apparatus for improved metal-insulator-semiconductor

1986-07-31

1988-03-01

Carroll, J.

357 24, 357 31, 357 32, 357 53, 357 54, 357 52, H01L 2978, H01L 2714, H01L 2940, H01L 2934

Patent

active

047290056

ABSTRACT:
An improved method and apparatus for reducing edge field enhancement in semiconductor devices such as metal-insulator-semiconductor devices is disclosed. The method comprises the step of biasing a buffer gate which overlies an insulation layer and an area of a substrate in which it is desired to reduce the edge field enhancement at a voltage exceeding the flatband voltage so that a buffered zone is created in the substrate. The apparatus consists of a substrate, a plurality of insulating layers overlying the substrate, at least one gate electrode formed on one of the insulating layers and a buffer gate formed on a second of the insulating layers. When the gate electrode is biased so that a potential well is formed in the substrate, the buffer gate is simultaneously biased so that a buffered zone which adjoins the potential well is formed. This buffered zone results in a decrease in the edge field enhancement observed at the edge of the potential well below the gate electrode and allows the apparatus of the invention to operate in an improved fashion. The method and apparatus of the invention may be incorporated into imaging systems, such as infrared imaging systems, with increased dynamic range.

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A. K. Sood et al "Improved Performance of Implanted n.sup.+ -p Hg.sub.1-x Cd.sub.x Te Photodiodes Using Insulated Field Plates", IEEE Electron Review Letters, vol. ELD-1 (1980) pp. 12-14.
G. G. Jambottzar, "Spaced Field Plate for Increasing Planar Junction Breakdown Voltage" IBM Technical Disclosure Bulletin vol. 19 (1976) pp. 478-479.

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